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New IP with EDK : how connect external NET ?

I am creating my own test IP and can't find the proper way to generate external NET connection with logic using graphics tools of EDK

how do I generate the "mytest_rx_pin" entries in system.ucf ? (In port flat view, I never had the choice to "make an external connection" in my tes_0 instance, as said in docs...)

my test is rather simple : I want access from microblaze to H13 button as in : value = XIo32_In(0x42000000); (value changes if buton is pressed)

my config is spartan3E starter kit and EDK 8.1.

user_logic.vhd

-=-=-=-=-=-=-= ...

signal data : std_logic; ...

IP2Bus_data(0) test_x,

Reply to
rponsard
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I reply to myself :

it is possible to manualy edit the MPD file and add a PORT ligne as needed

is there a better way ?

snipped-for-privacy@gmail.com wrote:

Reply to
rponsard

I just did this yesterday for the first time. I had EDK generate my peripheral and then I had to edit .ucf, .mhs, .mpd, peripheral.vhd, AND user_logic.vhd to add my clock and ADC lines. If you find a faster way please post.

Thanks, Clark

Reply to
Anonymous

I always edit these files manually (.mpd, .pao, .bbd and .vhd). AFAIK there is no better/faster way of do For peripheral creation, you must do the following:

Indicate the module name and destination, such as the XPS project or EDK repository in which the peripheral must be stored.

Select the bus interface to which the peripheral is targeted.

For OPB/PLB peripherals, select and configure IPIF services. These are common functions required by most peripherals. If you select this, reduce the amount of HDL code you write.

For FSL peripherals, select and configure the FSL bus interface and driver function.

-> Implement user logic in generated files. This requires the use of common HDL-based design flows.

Implement peripheral driver files. This requires the use of common software-based design flows.

Frank

Reply to
Frank van Eijkelenburg

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