Hi all, I'm new to the Xilinx FPGA FIR filter and would like to ask fo help. I have two (X and Y) channels and their frequency is about 10Mhz. Using 2 14-bits ADC with sampling 50Mhz. I have my Xilinx clock about 50Mhz.

How many taps for each channel is necessary for doing a cutoff frequenc of 10MHz?

How many bits should the coefficients length is? how to do a optima design?

I have to use FIR because my moving avaraging doesn't solve the problem.

What other terms I need to consider?

is my Spartan 3 xcs3s400 enough? 16 multipliers. is that 1 tap require 1 multiplier. If so, I would get a virtex II pro board.

At last, I want to say thank you for looking at my thread and I hope yo can answer my questions.

thanks again, Kenny,