FIR filter fpga help

Hi all, I'm new to the Xilinx FPGA FIR filter and would like to ask fo help. I have two (X and Y) channels and their frequency is about 10Mhz. Using 2 14-bits ADC with sampling 50Mhz. I have my Xilinx clock about 50Mhz.

How many taps for each channel is necessary for doing a cutoff frequenc of 10MHz?

How many bits should the coefficients length is? how to do a optima design?

I have to use FIR because my moving avaraging doesn't solve the problem.

What other terms I need to consider?

is my Spartan 3 xcs3s400 enough? 16 multipliers. is that 1 tap require 1 multiplier. If so, I would get a virtex II pro board.

At last, I want to say thank you for looking at my thread and I hope yo can answer my questions.

thanks again, Kenny,

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On a sunny day (Wed, 18 Oct 2006 11:46:44 -0500) it happened "cutemonster" wrote in :


This is free:

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Reply to
Jan Panteltje



frequencyof 10MHz?



Thanks, and I used this tool before. What I don't understand is th minimum taps that I need. Is the sampling rate ok? is the fpga clock ok? I have many fundamental questions that I could find from my textbooks.

thank you, Kenny,

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On a sunny day (Wed, 18 Oct 2006 14:09:06 -0500) it happened "cutemonster" wrote in :

Well, I am no filter expert but these parameters you mention, and the type of filter, depend on how steep the filter needs to be, and how much ripple is allowed, the phase response... So I cannot answer that with numbers. Also the speed of course, more speed more hardware basically.

Reply to
Jan Panteltje

The number of taps required depends on how sharp the transitions are in your filter characteristic, how much passband ripple you are willing to accept and how much stopband attenuation you need. You will need a filter design tool to design the filter (can be done by hand, but is extremely tedious), so when you get your hands on that tool you can play with the parameters to find a decent compromise.

As far as number of bits in the coefficient goes, that depends mostly on the amount of stopband attenuation you desire. Quantizing the coefficients changes the filter characteristic, and generally speaking the effect is manifested as peaks in your stopband. A good rule of thumb for the number of coefficient bits needed is you get about 5dB better stopband attenuation for each additional coefficient bit.

Whether a particular FPGA is satisfactory depends on your sample rate, the clock rate at which you can comfortably clock the FPGA (depends on your design skills), and the number of taps needed to realize the filter you desire. That said, the Spartan3 XCS3S400 should be fine as long as your filter is modest. You may have to pull some tricks if your filter turns out to be more than 16 taps such as symmetry folding or time multiplexing the multipliers to handle more than one tap per sample (this is where working with a multiplied clock really helps out).

Reply to
Ray Andraka






thank you for answering my question. I really appreciate it.


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You probably have ruled out IIR filters already, but I thought I'd mention them just in case.

---Matthew Hicks

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Matthew Hicks

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