Hey all
I saw this on an example design (on Xilinx ISE):
NET clkb PERIOD = 25ns; NET "clkb" LOC = A16;
what does it mean when it mention about the period 25ns? in the design, the clock at location A16 is actually 40Mhz (25ns). is this necessary for UCF file?
thx
That's a timing constraint to make sure that the tools place and route the design with a solution that will work at your desired 40 Mhz clock rate. It is necessary if you want your design to meet timing (ie if you want your design to work over temperature, voltage and process).
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