Field-Programmable Gate Arrays

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Camera link specification

Hi All, I have a project to get the image data by camera and want to convert them as grayscale information. The camera...
7 comments posted 20yrs
posted by ivanlimansyah
7 comments posted 20yrs posted by ivanlimansyah

PowerPC somehow unstable at 300 MHz

Hi ... I've got a Virtex2P-30 (sg6) and I'm trying to use one of the PowerPC-cores at 300 MHz (in a system much like xa...
7 comments posted 20yrs
posted by MSchoeberl
7 comments posted 20yrs posted by MSchoeberl

XC2V80005FF1517C

Does anyone know is this big FPGA is still being used in production? Thank you!
1 comments posted 20yrs
posted by tmoore
1 comments posted 20yrs posted by tmoore

Microblaze : FSL bus

Hi, I want to use the FSL bus to connect two microblazes together. Because I am not familiar with the FSL bus, I first...
4 comments posted 20yrs
posted by gerd.van.den.branden
4 comments posted 20yrs posted by gerd.van.den.branden

Spartan 3 Configuration Questions

I'm trying to configure a Spartan 3 via Slave Serial mode at power up. I'm storing the configuration file in SPI Flash...
9 comments posted 20yrs
posted by greg
9 comments posted 20yrs posted by greg

Virtex4 debug bitstream generation problem

Hello, I came accross what I think is a bug in virtex4 debug bitstream generation. In this mode, the two pad frames (82...
1 comments posted 20yrs
posted by jbnote
1 comments posted 20yrs posted by jbnote

Where is the XORCY in the synthesised file?

Hi, I am learning a simple 16 bits adder using VHDL: begin a1: process (CLK) variable count_a, count_b : std_logic_vect...
1 comments posted 20yrs
posted by rxjwg98
1 comments posted 20yrs posted by rxjwg98

Can ISE text editor generate CRLF line endings?

Is it possible to get the ISE 8.2i text editor to use CRLF for line endings on a Windows system? It seems to use LF onl...
3 comments posted 20yrs
posted by ej
3 comments posted 20yrs posted by ej

cross-post: newsgroup servers

Hi to every one, I'm sorry for the cross-post but I need information from both ng. I have problems with my server becau...
2 comments posted 20yrs
posted by alessandro.basili
2 comments posted 20yrs posted by alessandro.basili

Code synthesizes to one FPGA but not to another?

Hey everyone, I'm fairly new to VHDL and especially to synthesizing code to program an FPGA. For a class project, I dev...
5 comments posted 20yrs
posted by jay.wineinger
5 comments posted 20yrs posted by jay.wineinger

System ACE and remotely reconfiguring an XUP board?

I would like to remotely force a reconfiguration of my XUP board from CompactFlash by talking to the SysACE chip, perha...
3 comments posted 20yrs
posted by neil.steiner
3 comments posted 20yrs posted by neil.steiner