Spartan 3 Configuration Questions

I'm trying to configure a Spartan 3 via Slave Serial mode at power up. I'm storing the configuration file in SPI Flash and using a uP to read the Flash and send the configuration bit stream (and clock) to the FPGA. (I've considered using the FPGA Master Serial mode to clock the SPI Flash, and just using the uP to initiate the flash read instruction, but the hardware is not currently configured that way, so I want to get it working in the Slave Serial mode first on my current hardware.)

I've read Xapp 502 but it still leaves me confused on a couple of points.

  1. The app note says a .bit file contains header info that should not be downloaded to the FPGA, so I'm trying to use a .bin file. However, I thought the header information allowed the clock rate to be increased in the Master Serial mode. Does the .bin file also include that information? (If I try to use Master Serial mode later.)

  1. When I serialize the .bin file bytes into a bit stream, do I load the bits from each byte MSB or LSB first into the FPGA?

  2. When I finish loading the entire .bin file I wait for DONE to go high, and while waiting test if INIT is low (which indicates a CRC error). So far I never get a DONE high or an INIT low. Seems like I should get one or the other? Configuration works fine using Platform Cable USB (JTAG). M0,M1,M2 are configured correctly in Slave Serial mode.

Thanks for answers/suggestions.

Reply to
Loading thread data ... schrieb:

there is "File header" present in BIT file and BITstream header present in BIT and BIN (and other files)

it actually doesnt care if you dont strip the FILE header, the simplest is usually just take the .BIT file, and:

1 send it as is to the DIN, DONE=1? you are lucky 2 reverse bits in BIT, send to DIN DONE=1, if not something is wrong

one of 2 should work


Reply to

I don't understand what you are saying. Do you send the LSB first, or the MSB?


Reply to
fsdgsdf schrieb:

I try first either LSB or MSB, and the the other one. so I dont have to figure out what is the right one, within

2 trial attempts it must work.

its better approuch then selecting one of options and being sure its the correct one, then trying 23 times to figure out the bits need to be swapped.

if you write mydesign.bit on SD card in original not swapped form, then read it back then the bit order is the same as it needed to push into FPGA, if you get your bits from some other media (SPI flash, something else) you may have to swap bits. Again simplest method is not try fogure out the correct one, but just try 2 times, with both swap and noswap.


Reply to

Yes, the header is included in the .bit.

send byte by byte with LSB first

add more free CCLK edges until Done comes high !

Regards, Laurent

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Reply to
Amontec, Larry

Remember to clock some extra cycles to initiate the fpga..

Reply to
Morten Leikvoll

Which is fine as long as there are no other problems. If there are, it doubles the number of permuations of things that may be wrong...!

Reply to
Mike Harrison

sure. sending (or not) extra clocks is one possible issue. but trying the bit swap once says that there is one problem less to check at leat.


Reply to
Antti Lukats

Thank you. It is difficult debugging hardware and software together when there is more than one thing wrong at the same time. So I wanted to remove this variable.

I am already doing that.

Thank you. I'll keep looking for other signal problems.


Reply to

Compare your uP output to that of a working download cable?

Record the output of the uP and see if it really does what you expect?

Will it work if you slow down the load process? (RF issues)

Maybe you have to do some 16-32-64 bit swap etc.. ? (endian issues)

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