Latest threads in Field-Programmable Gate Arrays

Aurora IP core vs. RocketIO wizard

Xilinx has lost my account somehow so that I am unable to log on their web support page... so I thought I'd try it here...

1 19yrs

mbmsv

1 19yrs mbmsv

Influence of temperature and manufacturing to propagation delay

Hi, we are running in trouble with our curent design for a Xilinx Spartan 3 xc3s1500. It does signal processing and it...

25 19yrs

tom.reinemann

25 19yrs tom.reinemann

sending data across a 32 bit bus

How can I send a 256 bit data across a 32 bit bus/ Could any one please help me with how I can do this using verilog. Th...

2 19yrs

reshmid

2 19yrs reshmid

Why are there ModelSimAltera warning

Hi, The following is the first example in the DSP book written by U.Meyer Baese. I write a testbench in VHDL to have a...

1 19yrs

rxjwg98

1 19yrs rxjwg98

xilinx_device_details.xml <= which program create it?

hi, everyone, I run ISE in line cmds, i found that "xilinx_device_details.xml" was created automatically. Can someone t...

0 19yrs

uvbaz

0 19yrs uvbaz

FFT in VHDL (or Verilog) Tutorial

Hello, Can someone point me to simple implementation of FFT in VHDL(or Verilog) with testbench and good step-by-step de...

2 19yrs

confusedstudent001

2 19yrs confusedstudent001

problem about license of Modelsim in Altera quartus webpack

Hi, I installed Quartus II and it works except Modelsim on both my laptop and desktop computers. For desktop computer,...

4 19yrs

rxjwg98

4 19yrs rxjwg98

xupv2p

Helllo, Does anyone know about transfering data between two xupv2p boards, that is from one board to another? I apprecia...

8 19yrs

nmichou

8 19yrs nmichou

Xilinx ML310 programming failure

I was wondering if anyone using the ML310 is having similar issues as I am -- What I'm using: - Platform Cable USB - Xi...

0 19yrs

kunals.spam.account

0 19yrs kunals.spam.account

Running an application from external memory in Xilinx

Hello All, I figured out how to run an application from external memory in Xilinx. I have EDK ver 8.2.01i and an ML403...

0 19yrs

james.h.w

0 19yrs james.h.w

Nested Generate Statement in VHDL

Hi All, I am using a nested generate construct in my VHDL code to conditionally instantiate a component a number of tim...

4 19yrs

Sudhir.Singh

4 19yrs Sudhir.Singh

NTSC/VGA / Ethernet Advice for S3EBOARD from Digilent

I just bought the S3EBOARD from Digilent (http://www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD&Nav1=Products&Na...

3 19yrs

grant

3 19yrs grant

Compile error by Cadence NC-Sim

hi, everyone, I want to compile two VHDL-Code, and the Xilinx simprim library into my design. 1. hdl.var: DEFINE WORK w...

5 19yrs

uvbaz

5 19yrs uvbaz

IEEE 1149.6 support in Virtex-5

Hi Virtex-5 seems to support AC/differential signal debugging via JTAG scan but I am not finding any closer documentati...

0 19yrs

Antti.Lukats

0 19yrs Antti.Lukats

Seemingly random delays on Xilinx OSERDES

I have simulated the delays on Xilinx OSERDES using both the ISE simulator and ModelSimXE and find that the delay in se...

2 19yrs

bradsmallridge

2 19yrs bradsmallridge

Field-Programmable Gate Arrays

Worth reading in Field-Programmable Gate Arrays