hi, everyone,
I want to compile two VHDL-Code, and the Xilinx simprim library into my design.
- hdl.var: DEFINE WORK worklib DEFINE LIB_MAP($LIB_MAP, \ $XILINX/verilog/src/simprims => SIMPRIM_VER, \
src/fprint.vhd => FPRINT, \ src/fprint_body.vhd => FPRINT)
- cds.lib SOFTINCLUDE .../cds.lib DEFINE std ... ... DEFINE worklib /.../publib/worklib DEFINE SIMPRIM_VER /.../publib/simprim_ver DEFINE FPRINT /.../publib/fprint
- ncvlog.options
-messages
-status
-sv31a
-linedebug
-cdslib cds.lib // Use the specified cds.lib file
-hdlvar hdl.var // Use the specified hdl.var file
-logfile ncvlog.log // Files to be compiled: $XILINX/verilog/src/simprims/*.v
- ncvhdl.options
-messages
-status
-v93
-linedebug
-assert
-cdslib cds.lib
-hdlvar hdl.var
-logfile ncvhdl.log
// Files to be compiled: src/fprint.vhd src/fprint_body.vhd
- c-shell script under unix #!/bin/csh -f clear ncvlog -f ncvlog.options # Compile the verilog files ncvhdl -f ncvhdl.options # Compile the vhdl files
There are two points, i cant understand:
- fprint.vhd + fprint_body.vhd were compiled, but put to the WORK, however, i want it in FPRINT
- $XILINX/verilog/src/simprims/*.v cant be compiled, an error: ncvlog:
*E,BADFIL: invalid file: /design/software/XILINX/ISE/8.2i-SP1/verilog/src/simprims (not a regular file)
Thanks for your answer, :)
Regard, Cheng