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Seemingly random delays on Xilinx OSERDES

I have simulated the delays on Xilinx OSERDES using both the ISE simulator and ModelSimXE and find that the delay in serial output does not match the specifications in the user guide. Has anyone had a similar experience? There is suppose to be at least a one framing clock delay and a variety of serial clocks delay depending on the data width.

Moving the design to hardware I find a seemingly random delay by comparing the output of an OSERDES to a framing clock (CLKDIV) outputted by an ODDR.

Only by outputting the CLKDIV signal by another OSERDES did I find any synchonization between CLKDIV and the data:

cam_oserdes_xclk: cam_link_out_sdr_oserdes port map( clk => cam_clk_280, -- in clkdiv => clkdiv, -- in data => "1100011", -- in 7 bits q => xclk ); -- out

This works great. Did anyone else have an issue using ODDR?

Brad Smallridge aivision

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Brad Smallridge
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Brad

I am also interested in this, as I am just completing a design using OSERDES in Virtex 4 right now - haven't fully simulated yet though. In your case, where is you clk coming from? Is it coming from a clock capable input pin, through IBUFDS and BUFIO (then BUFR to create clkdiv), or is it coming from an internal global clock (eg through a DCM?) The latter seems to be allowed but I can't see much documentation, so that may be the cause of the skew...

Also, whenyou say "random delay", do you mean a random skew between the delay of several OSERDES (e.g. several pins on a fast parallel output bus), or that the delay varies from one hardware trial to the next, or just seems non-deterministic wrt the ODDR output?

Not many answers so far I'm afraid, but I will post my own results soon if it is helpful.

Tom

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Tom

From a DCM and skew might not be the right word for it because it's several clk periods difference.

Good question and I wasn't clear. It's non-deterministic on power-up. I am sort of guessing here because I don't have a scope good enough to see these frequencies, however, I have one board talking to another and it seems as if when the transmitting board is repowered or reset, the clkdiv and clk data phase get randomly assigned. I have no problems, thank goodness, if I use all OSERDES transmitters, instead of using OSERDES for data transmitters and an ODDR for clkdiv.

Please do post. Thanks.

Brad Smallridge AiVision

Reply to
Brad Smallridge

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