Hi All, I am using a nested generate construct in my VHDL code to conditionally instantiate a component a number of times. I have a constant that specifies how many of these components need to be generated. If it is zero then none should be generated. I am catching the zero case by having a compare to zero condition in the outer generate statement.
my code looks like
gen_tx: if N_TX > 0 generate gen_tx_inst: for i in 0 to N_TX-1 generate tx_inst: tx port map(...); end generate gen_tx_inst; end generate gen_tx;
Now if I set N_TX to zero, Modelsim compiler issues a warning about the inner generate, saying "Range 0 to -1 is null". I understand that the inner range would be 0 to -1 if I set N_TX to 0, thats what I have been trying to catch by having an outer generate.
Can I safely ignore this warning message? Would the synthesis & PAR tools (Xilinx) misbehave because of this? Does anyone have a better method of doing this?
Thanks in advance. Sudhir