Nested Generate Statement in VHDL

My belief is that you can safely ignore the warning. The VHDL compiler will insist on 'compiling' or at least parsing the innards of a generate even if the condition fails, which can be quite annoying! I'm sure there's a good reason - I'm just a big fan of C macros and I wish that VHDL had the same. Yes, I am aware of pre-processors but it's not really an option when you're writing code for customers.

It's also very annoying that generate *requires* a label, and that it doesn't have an 'else'!

I'm not sure you need to even catch the zero case - the inner loop should suffice!?!

Regards,

Hi Mark, Thanks for your reply. Yeah its really annoying that VHDL doesn't have the if & else construct for generate.

I also find the different syntaxs for if else type selection based on whether its a concurrent statement or inside a process, quite annoying.

Thanks. Sudhir

Mark McDougall wrote:

See Peter Ashenden's proposal on generate statements:

And the VHDL2006 standard:

For some reason the cleaned up P1076-2006-D2.11.pdf document was removed from the accellera's website, not sure why. The above zip file contains the document with all the corrections shown.

If you want "if & else" generate support for VHDL then email your simulator vendor and ask them when this standard will be supported. The more emails they get the more likely it is they will support it. I have already emailed Modeltech and they said they are working in it.....

Hans

Hans, The draft you want is 3.0. It is not a public document. To get it you must join the Accellera VHDL TSC (note this does not require money and hence it is more like registering). To register, go to

The copyright owner is IEEE and they forbid giving away the standard to people other than those who are participating in the revision. Hence, when you register, you become a participant and you can get a copy. :) Since there is not a simple standards developers guide, it took a little time to resolve this and realize that making it public was not ok - even when Accellera developed the changes.

This has more truth than you may believe.

Every revision a vendor makes to their tool is an investment. WRT standards, they want to know their investment is a good one. Having users interested and asking when it will be done is a good indication that it is a good investment (and a threat because if they fail to do it, you might buy someone else's simulator or synthesis tool).

Cheers, Jim