Field-Programmable Gate Arrays

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simulating two-dimensional array in vhdl

Hello all, I am trying to use a two-dimensional array in the port of a vhdl program as follows: entity tree_adder is po...
2 comments posted 19yrs
posted by ruben.gue
2 comments posted 19yrs posted by ruben.gue

regarding changing serial data out to LVDS form

hi all, i have serial data out in my design and i need to convert it to LVDS signal how can i covert it to LVDS . my en...
4 comments posted 19yrs
posted by ekavirsrikanth
4 comments posted 19yrs posted by ekavirsrikanth

MPMC2: MPMC2 with DDR2 SDRAM

Hi, Has anyone successfully used MPMC2 as the memory controller for DDR2 SDRAM? I used it to interface with the Micron'...
17 comments posted 19yrs
posted by czinyan1983
17 comments posted 19yrs posted by czinyan1983

Virtex-4 : OCM

Hi, I was trying to run a C program from the OCM BRAM. I have not incorporate external memory to my design yet. I manag...
2 comments posted 19yrs
posted by czinyan1983
2 comments posted 19yrs posted by czinyan1983

Question about adder structure

Hi, In the book "Digital signal processing with field programmable gate arrays" (1st edition) written by U.Meyer Baese,...
1 comments posted 19yrs
posted by rxjwg98
1 comments posted 19yrs posted by rxjwg98

Xilinx platform cable USB

Hi, It might be a naive question, however, I just want to make sure. Is Xilinx new USB JTAG backward-compatible with ol...
3 comments posted 19yrs
posted by mloulah
3 comments posted 19yrs posted by mloulah

Question about Maxplus 2?

Hi, I have the book written by Uwe Meyer "Digital Signal Processing with FPGAs", 1st edition. Now, I want to learn the...
1 comments posted 19yrs
posted by rxjwg98
1 comments posted 19yrs posted by rxjwg98

Xilinx USB cable - can't install driver

This used to work! I've had it put away for a couple of weeks, and now when I plug in the Platform cable it tries to re...
3 comments posted 19yrs
posted by zwsdotcom
3 comments posted 19yrs posted by zwsdotcom

SOPC builder/Nios2: booting from custom NV-RAM

When the Nios reset vector points into Altera-provided CFI flash SOPC builder automayically adds following lines to the...
0 comments posted 19yrs
posted by already5chosen
0 comments posted 19yrs posted by already5chosen

Xilinx XC9500 Jtag instructions?

Does anyone know where to find the XC9500 Jtag programming instructions? I have one for the XCR3000 (cool runner) and l...
4 comments posted 19yrs
posted by me
4 comments posted 19yrs posted by me

Pad to Setup, Clock to Pad

I am new to FPGA design so I'm sure this is a very basic question. Is there a rule of thumb when using these constraint...
7 comments posted 19yrs
posted by portisi
7 comments posted 19yrs posted by portisi

Power-on reset

Is there a dedicated power-on reset function in Verilog? What I want to achieve is that my own reset functionality will...
8 comments posted 19yrs
posted by borge.strand
8 comments posted 19yrs posted by borge.strand

EDK : path set

Hi, After installing EDK 8.1i and update to SP 2, I meet this error when run the EDK: error: general error in xps-sdk l...
1 comments posted 19yrs
posted by airthang
1 comments posted 19yrs posted by airthang

SPI module in FPGA

I am trying to write code for a SPI circuit (in VHDL) for the Altera Cyclone II FPGA. I think I understand the implemen...
6 comments posted 19yrs
posted by helluvanengineer
6 comments posted 19yrs posted by helluvanengineer