Field-Programmable Gate Arrays

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Xilinx EDK Problem

Hi I have a design with a Power PC that I am trying to put through ISE. Th problem I have is that I get the following e...
1 comments posted 19yrs
posted by maxascent
1 comments posted 19yrs posted by maxascent

Constraining timing analyser when using two DCMs

Tool = ISE 8.2i Target = Spartan 3 xc3s400-4tq144 I'm using an external 50 MHz oscillator and a single DCM to generate...
3 comments posted 19yrs
posted by ajholme
3 comments posted 19yrs posted by ajholme

Voltage prorating for Spartan 3

Tool = ISE 8.2i Target = Spartan 3 xc3s400-4tq144 I created a prorated VOLTAGE constraint using the GUI constraints edi...
1 comments posted 19yrs
posted by ajholme
1 comments posted 19yrs posted by ajholme

DCM Jitter

Tool = ISE 8.2i Target = Spartan 3 xc3s400-4tq144 I'm using an external 50 MHz oscillator and a single DCM to generate...
8 comments posted 19yrs
posted by ajholme
8 comments posted 19yrs posted by ajholme

Problems connecting MicroBlaze to custom IP

Hi, I'm trying to connect a MicroBlaze system build in EDK to a custom periphal core. I am using Atmark's Suzaku board...
5 comments posted 19yrs
posted by cschleiffer
5 comments posted 19yrs posted by cschleiffer

query

Can anybody throw light on vqm editor 1)Back annotation on FPGA of quartus II 6.0.I am confused with that options .Impo...
2 comments posted 19yrs
posted by vsrpkumar
2 comments posted 19yrs posted by vsrpkumar

Altera configuration with microcontroller

I'm looking at the cost of serial configuration devices from Altera and am a little shocked at how expensive they are....
5 comments posted 19yrs
posted by nevo_n
5 comments posted 19yrs posted by nevo_n

Cache trouble in XPS

Hi When using data cache in xilinx platform studio, to cache an external DDR memory(64MB) on the OPB bus and a BRAM blo...
0 comments posted 19yrs
posted by RUNE_dahl
0 comments posted 19yrs posted by RUNE_dahl

Cache trouble in Xilinx XPS

Hi When using data cache in xilinx platform studio, to cache an external DDR memory(64MB) on the OPB bus and a BRAM blo...
0 comments posted 19yrs
posted by RUNE_dahl
0 comments posted 19yrs posted by RUNE_dahl

Aurora and Chipscope

Hi, I am using aurora software to create a core to move data from the pc to xupv2p board to another xupv2p board and I...
0 comments posted 19yrs
posted by nmichou
0 comments posted 19yrs posted by nmichou

Virtex 4 Internal Tristate (BUFT)?

Hello, I was just browsing the Xilinx Libraries Guide pdf in search of BUFT component. However, it is not mentioned any...
2 comments posted 19yrs
posted by Ih8teSpam
2 comments posted 19yrs posted by Ih8teSpam

Xilinx DDR2 IP core performance

Hi when looking at EDK OPB_MCH_DDR2 memory controller datasheet then it looks like each access to DDR2 memory takes abo...
1 comments posted 19yrs
posted by Antti.Lukats
1 comments posted 19yrs posted by Antti.Lukats