Hello,
I was just browsing the Xilinx Libraries Guide pdf in search of BUFT component. However, it is not mentioned anymore in the 'Virtex 4 Libraries Guide for HDL designs'. I was looking into them to optimize wide muxes and a bus traversing the complete FPGA fabric. Are tristates left out of the Virtex4? Is there an alternative? What could be the motivation for such an architectural change?
Best Regards, Koen.
Hi, There are no BUFT in Virtex-4 because of their big delays. Use multiplexers instead.
Best Regards
The internal tristates have been gone for a while. Other dedicated resources do a better job even for extremely wide busses. Many designs didn't use the slower, dedicated tristates in the older generation parts so why keep designing the little-used functionality when the generic device provides a better solution?
If you're using HDL, you can still implement tristate logic internal to your chip (assigning a driven value or z across your bits) and the synthesis will do the translation to multiplexers for you. No primitive needed. You may get an INFO or WARNING message depending on your synthesizer.
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