Field-Programmable Gate Arrays

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ISE 8.2 & XC9500XL family

Hello, as many people over this world, I have a problem. The problem is the connection beetween a CPLD and the WEBPACK...
3 comments posted 19yrs
posted by bit_vector
3 comments posted 19yrs posted by bit_vector

CORDIC FM Demodulation

Hello, I know that it is possible to demodulate an FM signal using a CORDIC ATAN core and the subtracting the current o...
8 comments posted 19yrs
posted by ma
8 comments posted 19yrs posted by ma

I2C "READ" Setup/Hold Requirement

Hello For the I2C read, the step by step, the algorithm is: 1). write slave address+write bit 2). write register addres...
2 comments posted 19yrs
posted by markus_1401
2 comments posted 19yrs posted by markus_1401

Spartan 3E-Kit

I found the thread about this kit but cannot write there, since it is more than 60 days old. I am seeking for an empty...
13 comments posted 19yrs
posted by spartanius
13 comments posted 19yrs posted by spartanius

V5 LXT PCIe Block simulation

I am trying to simulate PCI Express Endpoint Block 1.1 generated by coregen in ModelSim SE. I get the following errors...
1 comments posted 19yrs
posted by sovan.kundu
1 comments posted 19yrs posted by sovan.kundu

timing constraints

In the cyclone devices, How to set parameters like tco,tsu,th,tpd.I am not using any M4K RAMS or DSP blocks.I am using...
2 comments posted 19yrs
posted by vsrpkumar
2 comments posted 19yrs posted by vsrpkumar

What's wrong with my tcl example in Quartus?

Hi, I am new to tcl and quartus. When I try to follow the tcl example on page 2-2, Quartus II handbook, vol. 2, I canno...
2 comments posted 19yrs
posted by rxjwg98
2 comments posted 19yrs posted by rxjwg98

Spartan 3 Starter Kit .mcs upload problem

Hi, I have a problem in uploading an .mcs file from the Spartan 3 Starter Kit reference designs to the flash prom. Spec...
1 comments posted 19yrs
posted by jboehm
1 comments posted 19yrs posted by jboehm

DDR_SDRAM_VHDL_models

Does anynone know where can I find VHDL models for DDR-I SDRAM modules? I have an XUP board and I want to run some simu...
2 comments posted 19yrs
posted by
2 comments posted 19yrs posted by

DDR_VDHL_models

Does anynone know where can I find VHDL models for DDR modules? I have an XUP board and I want to run some simulations...
3 comments posted 19yrs
posted by
3 comments posted 19yrs posted by

ISE Synthesize Properties box

When I try to open the XST properties dialog box in ISE, the box appears but the options don't (i.e. an empty box). Has...
0 comments posted 19yrs
posted by enquiries
0 comments posted 19yrs posted by enquiries

Parallax Stratix Smartpack accessories?

Parallax, the company that makes those nifty little BASIC stamps, is (or was) selling off the last of the Cyclone and S...
1 comments posted 19yrs
posted by jshamlet
1 comments posted 19yrs posted by jshamlet

Differential to single ended convertion in FPGA

Hi, I want to convert a differential digital signal to single ended signal. But, because of skew, the positive and nega...
0 comments posted 19yrs
posted by prathap.ap
0 comments posted 19yrs posted by prathap.ap