Problems connecting MicroBlaze to custom IP

Nov 23, 2006 5 Replies

Hi,



I'm trying to connect a MicroBlaze system build in EDK to a custom periphal core. I am using Atmark's Suzaku board [1]. It is shipped with an example project which I would like to extend via FSL. Here is what I did:


- Added two FSL cores and connected them to the MB



- Changed the ports for my periphal to "make external"



My intention is to import the EDK project into ISE later on to connect it to my system. The instantiation template looks fine but when I try to generate the netlist of the processor system I get the folllowing error message:



[snip]
fsl_v20 (fsl_from_mb) -
> X:\Controller\EDK\xps_proj.mhs line 332 - 1
> master(s) : 0 slave(s)
> ERROR:MDT - fsl_v20 (fsl_from_mb) -
> X:\Controller\EDK\xps_proj.mhs line 332 - must
> have atleast 1 slave assigned!
> fsl_v20 (fsl_to_mb) - X:\Controller\EDK\xps_proj.mhs
> line 342 - 0 master(s) : 1 slave(s)
> ERROR:MDT - fsl_v20 (fsl_to_mb) -
> X:\Controller\EDK\xps_proj.mhs line 342 - must
> have atleast 1 master assigned!
>
> Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
> ERROR:MDT - platgen failed with errors!
>
> make: *** [implementation/microblaze_i_wrapper.ngc] Error 2
[snap]

The FSL master and slave ports will be connected in ISE, of course. Is there any way to override the error message? Is there a better solution? EDK and ISE are the latest version with all service packs/patches applied...



Thanks in advance, cheers /Chris



[1]
formatting link

Christian Schleiffer schrieb:

one solution is to make the MB FSL ports external, in that case you have no FSL bus in EDK, this works for sure, but you have to implement the FSL bus and-or fifos in ISE toplevel then

Antti

Good point. It should be quite simple to implement FSL myself, but I think I even saw some source files somewhere in the EDK directory...

Another solution is making FSL BUS ports external, leaving the other side connected to MB. Thus you don't need to implement FSL FIFOS.

Zara

Zara schrieb:

Hi Zara,

this is exactly what I tried to do.

^^^^^^^^^^^^ Maybe that should have been "...ports _to_ my..." ;) My fault. Thanks anyway.

/Chris

Antti,

I found the instantiation template for the FSL bus and it took me about

5 minutes to make it working your way.

Thanks very much /Chris

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