1. Home
  2. Field-Programmable Gate Arrays
  3. Division of a (rather large) Gate level Combinational Design

Division of a (rather large) Gate level Combinational Design

Hi, This is the second time I am posting to this group within a week, but I think that this necessitates another thread. (Through google groups my original thread can be accessed at

formatting link

My problem is that I am trying to synthesize gate level combinational circuits that have a large number of signals. (I actually did not realize how large it was till Thomas and Andreas explained it to me in the previous thread.) My circuit probably uses around 40 K gates, but a lot more signals.

From the discussion in my previous thread, I realized that the synthesis tools (I use XST) have/has problems with (1) large number of signals (2) large combinational paths

I don't really mind the synthesis time - rather I am concerned that I run out of memory. (I hit 4 GB - and I don't have the 64 bit version.)

I would also like to mention that as far as the number of gates is concerned, I am sure that my design would fit onto one FPGA, with a utilization of less than 50%. (Using the xc2v6000-4.)

Does anyone have an idea how I can get this to synthesize? Partial Synthesis (i.e. synthesis of parts of my design separately) was suggested to me in my previous post, but I could not figure out how to do this in XST. (I can dump out the NGC files for different parts of my design - but how do I combine them?)

If long combinational paths are an issue, is there a way to break up a long combinational path (i.e. add registers or latches etc.). I thought about latches - but then deciding where to insert the latches is a big question. (I don't mind compromising on timing if this is a factor of

2, 3 or even 10, but I don't want this running into a factor of 100's or 1000's.)

Thanks to all those who may have some ideas. O.O.

Reply to
olson_ord
Loading thread data ...

Can you figure a way to functionally break up your design? The only huge "combinational" designs I've known of were either 1) incorrect or 2) part of a genetic algorithm development. Chances are that your design is significantly more complex than it needs to be. Rather than performing everything in one large equation, can you divide it up into functional parts that can give you your goal in several clocks rather than all at once?

The idea is the first, most important part of your design. Implementation gets you toward reality. Ask yourself what the hardware can do and use that as a guideline for how to partition your design in functional pieces that can give you what you need over several clocks.

Good luck.

formatting link

Reply to
John_H

Dear John, I actually mentioned this in my previous thread - but I think I need to repeat it here. (I don't have much experience posting to news groups.)

I am a student, without much experience of synthesis. My task was to make some modifications (i.e. insert faults) to the ISCAS benchmark circuits and synthesize them to the FPGAs. I read the circuits using the ISCAS benchmark format - made my changes to the circuit structure and dumped out the VHDL.

As my initial circuit is combinational and a gate level netlist - it cannot be functionally divided in anyway. I can of course group neighboring gates into higher level entities - but I don't think that this would make things easier for the synthesis tool.

I am not sure if this clarifies some aspects regard> Can you figure a way to functionally break up your design? The only huge

Reply to
olson_ord

What kind of gates do you have in your original netlist? Is it simple nand/and/or/nor-gates with few inputs?

If you have that kind of gates with 4 or less inputs it is easy to map one gate to one LUT. In that case you will feed a netlist to the synthesizer which is already composed of primitives so the synthesizer will not be able to optimize the design much and therefore should be able to run with less effort (hopefully).

/Andreas

Reply to
Andreas Ehliar

Hi Andreas, Though the number of signals in my design is large - I am sure that most of the gates are simple and have less than 4 inputs. I am not sure how I should map a gate to a LUT. Could you show me an example how to do that? (Right now XST does that for me - but I would be glad to specify that myself.) An example of a gate in my design looks like

And_2_282_1319 : node_R1207_U134_Cell_1282

Reply to
olson_ord

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.