Hi
when looking at EDK OPB_MCH_DDR2 memory controller datasheet then it looks like each access to DDR2 memory takes about 30 system clock cycles (60 memory clocks)
so maximum bandwith when reading bursts is about 50MB/s and even less when doing random reads, this sounds like EXTREMLY low performance, I wonder if the datasheet timings are wrong, or maybe the timing is fixed in EDK 9.1?
Antti