Hi
When using data cache in xilinx platform studio, to cache an external DDR memory(64MB) on the OPB bus and a BRAM block, I get some bad errors. The program runs without a hickup when the data cache is only enabled for the BRAM, but when enabled for the DDR memory, faulty data is read from memory. The data space cached is only the DDR memory and the BRAM, so no other hardware should be able the mess up the cache by changing the data on the other side of the cache.
I have just enabled the caches with the lines: XCache_EnableICache(0x00000001); XCache_EnableDCache(0x80000001);
I expected this to be enough, but I have also tried to invalidate every data cache line before running my program, but without any luck.
What am I missing?