Hi,
I'm working on a partial reconfiguration design and need to validate an assumption.
This question isn't directly releated to partial reconfigration, so don't let that scare you away.
I have a MicroBlaze created in EDK 8.2 that I must be integrate into a top level design created in ISE 8.2. I'm using the Virtex II-Pro.
The methodology is to take the system.vhd generated by EDK during netlist generation and add these component declarations and instantiations to the top level design. In a partial reconfiguration design clock primitive must be in the top level design. However, the system.vhd file uses wrappers for DCMs. Here's my question...am I removing the DCM wrapper correctly?
I remove the wrapper component declarations by commenting them out (I only show one here):
-- component dcm_0_wrapper is
-- port (
-- RST : in std_logic;
-- CLKIN : in std_logic;
-- CLKFB : in std_logic;
-- PSEN : in std_logic;
-- PSINCDEC : in std_logic;
-- PSCLK : in std_logic;
-- DSSEN : in std_logic;
-- CLK0 : out std_logic;
-- CLK90 : out std_logic;
-- CLK180 : out std_logic;
-- CLK270 : out std_logic;
-- CLKDV : out std_logic;
-- CLK2X : out std_logic;
-- CLK2X180 : out std_logic;
-- CLKFX : out std_logic;
-- CLKFX180 : out std_logic;
-- STATUS : out std_logic_vector(7 downto 0);
-- LOCKED : out std_logic;
-- PSDONE : out std_logic
-- );
-- end component;
--
-- attribute box_type of dcm_0_wrapper: component is "black_box";