1. Home
  2. Field-Programmable Gate Arrays
  3. Quartus II: Back-annotating bidir's gives two entries per pin...

Quartus II: Back-annotating bidir's gives two entries per pin...

Hello Group.

Not being that familiar with Altera's Quartus II, and it may be a beginners problem... Anyways... I'm compiling a VHDL-based design for the MAX-II EPM1270F256C5, which Ifinally managed to get error-free. When trying to back-annotate the Fitter's suggestion for the pin placing, the Pin Planner's list section actaully states two entries for the same physical pin and signal like this:

mpifdX[7] PIN_J14 mpifdX[7]~0 PIN_J14

I have run the Remove Assignments before the Back-annotation The signals giving this problem are always and ONLY the bidir's.

- Has anyone seen something similar and can give an explanation...?

Thanks i advance.

Jesper.

Reply to
Jesper.Kristensen
Loading thread data ...

These are internal signals, which represent the input (or OE, I'm not sure) and the output of the pin. They are automatically created by the synthesizer. In the pin planner, you should assign a pin location only to the name without the tilde. Avishay

Reply to
avishay

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.