Hi I want to connect an LVDS output from a Stratix II FPGA to a Camera Link frame grabber, but I can't figure out how I should configure the altlvds megafunction to the correct clock setting. Are they at all compatible?
Thanks, Avishay
FPGA to Camera (Channel) link
Dec 06, 2006
3 Replies
Avishay,
Yes, they are compatible. I have done this in both the Cyclone and Stratix families, both using the MegaWizard and building my own interface. The MegaWizard is pretty straight forward. What difficulties are you experiencing?
CamerLink is made up of 3 banks (base, medium, and full) of 4 lanes with a serialization factor of 7 for each lane. Each bank has an associated clock, which most newer grabbers can handle up tp 85MHz. All you have to do is tell the MegaWizard how many lanes, what the serialization factor is, and the speed of the data. The timing, when using the MegaWizard, is all done under the hood.
Rob
The altlvds Megawizard requires me to specify the data alignment to the input clock and the output clock. What are the values you entered?
Avishay
0 (edge aligned) for both see page 8 of this pdf for a picture:
formatting link
good luck
avishay wrote:
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