Field-Programmable Gate Arrays

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help with Xilinx LVDS syntax

I apologize if this questions has been answered already. I was unable to find an answer in my search through this group...
0 comments posted 19yrs
posted by morgank
0 comments posted 19yrs posted by morgank

Clock phase shift

Hi, I need to phase shift (180 deg) an output clock(100MHz) , I have an option of using DCM and with this it is possibl...
10 comments posted 19yrs
posted by ashish.shringarpure
10 comments posted 19yrs posted by ashish.shringarpure

Xilinx PLB IPIF

Hi, Is it possible to initiate 32 bit burst transactions on IPIF interface in Xilinx PLB-IPIF ? I am currently using 64...
0 comments posted 19yrs
posted by ashish.shringarpure
0 comments posted 19yrs posted by ashish.shringarpure

EDK 8.2, MDM, and ChipScope....

Alright....here we go. I was working with an EDK 8.2 project that had both an MDM module and ChipScope connected. ChipS...
5 comments posted 19yrs
posted by mottoblatto
5 comments posted 19yrs posted by mottoblatto

Altera starter kits

I'm looking into buying the fpga and/or cpld starter kits. I was wondering if the logic chips can be taken out of the de...
9 comments posted 19yrs
posted by ericwan78
9 comments posted 19yrs posted by ericwan78

query in gate level simulationin quartus s/w 6.0

I have two problems in verilog gate level simulation 1) I want to preserve hierarchy between entity.Where will be this...
1 comments posted 19yrs
posted by vsrpkumar
1 comments posted 19yrs posted by vsrpkumar

Timing constraings: min delay?

Is there a mindelay constraint keyword or something similar? My fpga is producing 1 byte with a clock signal going to t...
3 comments posted 19yrs
posted by seabass950
3 comments posted 19yrs posted by seabass950

First Look at QuartusII 6.1

I just downloaded from Altera's website QuartusII 6.1 and tried it out. I was disappointed that they didn't include any...
3 comments posted 19yrs
posted by dereks314
3 comments posted 19yrs posted by dereks314

Usage of BUFIO in Virtex 4?

Is there any advantage of using a BUFIO/BUFR's for driving IOB FF's versus a BUFG? After looking through that section i...
8 comments posted 19yrs
posted by killerhertz
8 comments posted 19yrs posted by killerhertz

Xilinx MPMC2 "External Ports" question

Hi all, Has anyone ever had success routing an NPI port of the MPMC2 controller to an External Port of a PPC based syst...
13 comments posted 19yrs
posted by ehenciak
13 comments posted 19yrs posted by ehenciak

Virtex-4 ML403 16x2 LCD

HI all, I am a student. I am new to verilog and FPGA. I have a question. How do I use the 16x2 LCD which is on the deve...
1 comments posted 19yrs
posted by shelai
1 comments posted 19yrs posted by shelai

RLOC weirdness

I'm just wondering if anyone here has seen the same problem I'm running into. I have a design where I'm playing around...
5 comments posted 19yrs
posted by ehliar
5 comments posted 19yrs posted by ehliar

Creating a single logical netlist...

Here's a summary of my problem: I have multiple ngc files, e.g.: top.ngc support1.ngc support2.ngc support3.ngc "top" i...
1 comments posted 19yrs
posted by robin.bruce
1 comments posted 19yrs posted by robin.bruce