differential I/O with ISE 8.2 / spartan3E

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- rponsard
  
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posted
17 years ago

Thu, Dec 7, 2006 10:47 AM

I am new to fpga design... and don't know the good practice to handle differential I/O.

I am right using OBUFDS and IBUFDS component ?

I have errors with ISE8.2 and my differential pairs (rx_pin and tx_pin) :

I greatly appreciate any helps... or a link to example for S3E starter kit

Unable to combine the following symbols into a single DIFFS component: PAD symbol "rx_pin_n" (Pad Signal = rx_pin_n) SlaveBuffer symbol "i_b/SLAVEBUF.DIFFIN" (Output Signal = i_b/SLAVEBUF.DIFFIN) Each of the following constraints specifies an illegal physical site for a component of type DIFFS: Symbol "rx_pin_n" (LOC=E8) Please correct the constraints accordingly. ucf:

NET "rx_pin_p" LOC = "F8" | IOSTANDARD = LVDS_25 ; NET "rx_pin_n" LOC = "E8" | IOSTANDARD = LVDS_25 ; NET "tx_pin_p" LOC = "D7" | IOSTANDARD = LVDS_25 ; NET "tx_pin_n" LOC = "C7" | IOSTANDARD = LVDS_25 ;

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- Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
  
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posted
17 years ago

Thu, Dec 7, 2006 5:28 PM

[... snip ...]

There are a few coding examples in the following E-mail that might prove useful. The code applies for Spartan-3, Spartan-3E, and the new Spartan-3A.

XAPP491: Inverting LVDS Signals for Efficient PCB Layout in Spartan-3 Generation FPGAs

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You can download the design examples directly from the following link.

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--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3 Generation FPGAs

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E-mail: snipped-for-privacy@xilinx.com

--------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.

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posted
17 years ago

Thu, Dec 7, 2006 9:56 PM

thanks, I already got xapp941.pdf but I still have trouble configuring those diff. I/O, now with VCC0 =

3.3V and diff LVDS2.5

ISE can't place : Phase 1.1 ERROR:Place:311 - The IOB tx_pin_p is locked to site PAD17 in bank 0. This violates the SelectIO banking rules. Other incompatible IOBs may be locked to the same bank, or this IOB may be illegally locked to a Vref site. Phase 1.1 (Checksum:98d76b) REAL time: 5 secs

xilinx answer database tells : Solution 1: This is a legal placement in hardware. However, the software currently does not allow this placement. LVCMOS15, LVCMOS18, and LVCMOS25 inputs must be in a bank with a matching VCCO level. These overly restrictive banking rules will be fixed in 9.1i, which is scheduled to be released in Winter 2006.

In the meantime, if you want to place one of these standards in a bank with a higher VCCO level (for example, an LVCMOS25 input in a bank with VCCO=3.3V, or an LVCMOS15 input in a bank with VCCO = 2.5V), you can modify the IOSTANDARD in the FPGA Editor and run BitGen without the DRC check (bitgen -d).

could you be more verbose about this solution ; aka

- how use FPGAEditor to change IOSTANDARD

- where can I configure bitgen w/o DRC