regarding -ve slack while doing post PAR timing analysis

A better option to start with is to (a) look at the static timing report (b) analyse and understand what is the slowest path in your circuit (c) redesign that part of your circuit so it has fewer logic levels between synchronous elements and thus runs faster (d) re-run MAP/PAR (e) If timing is not met, goto (a) and repeat until it is.

Fiddling with PAR options should be the last resort, not the first thing to try, unless you have very marginal timing. In your case (-1ns slack on

155MHz clock) you are off by 15%, which is far from marginal and indicates that the problem lies with the design.

-Ben-

hi all,

i am using spartan 3e fpaga xc3s100e -4 speed grade i have a problem while i am doing PAR after that post PAR static timing analysis i am getting -ve slack as my design needs 155mhz clock internal i am using DCM and i am generating that clock and that CLK2X_BUF of DCM is volating and as a result i am getting -ve slack about 1ns i have tried optins like

place and route effort level medium....

palce and route mode -> multipass route...

and other optins that are there in timing closure report............

but still i am getting -ve slack so i tried option of changing speed grade -5 that time slack is meetig but i have spartan 3e fpga which is xc3s100e -4 grade ........

so i tried false path option ........ but in my design timing is critical so i need to meet timing as false path will ignor that path i am not sure whether i will get actul timing slack (0 or +ve) in realtime on board...........

so anybody can plz help me in finding the solution for this and i have a doubt whether spartan 3e xc3s100e will support freq of 155mhz ............

regards srik