Field-Programmable Gate Arrays

gtkwave 3.0.18 for win32

Hi, I updated the GTKWave for Win32 port I am maintaining. It's at 3.0.18 now. The missing cygwin dll problem is fixed....

3 comments posted 19yrs

posted by kal*

3 comments posted 19yrs posted by kal*

Xilinx SYSTEM_JITTER, INPUT_JITTER Questions - Part II

How are these used in the case of FROM TO specs? For example, CLK In goes to a DCM, the CLK0 and CLK180 are used as CLK...

0 comments posted 19yrs

posted by sanjay112

0 comments posted 19yrs posted by sanjay112

Using SYSTEM_JITTER and INPUT_JITTER for timing analysis.

This is what I had in the ucf - > SYSTEM_JITTER = 300 ps; > > NET fpga_clk100 TNM_NET = TNM_fpga_clk100; > TIMESPEC TS_...

0 comments posted 19yrs

posted by sanjay112

0 comments posted 19yrs posted by sanjay112

Adding Jitter

Why do we do a quadratic add of jitter when calculating total jitter. For example, with an input jitter of +/- 100 pS,...

1 comments posted 19yrs

posted by sanjay112

1 comments posted 19yrs posted by sanjay112

Virtex-II Pro: Reading/Writing data with Compact Flash

Hello, We are using the Xilinx Virtex-II Pro Developement System XUP-V2P. Our objective is to read a binary file that c...

8 comments posted 19yrs

posted by abright52

8 comments posted 19yrs posted by abright52

Virtex-V MGT SONET alignment

Hi! Does anybody here have experience with Virtex-4 MGTs in SONET alignment configuration? We turn of ENPCOMMAALIGN and...

1 comments posted 19yrs

posted by news

1 comments posted 19yrs posted by news

Port OS: Error when generate the Libraryies and BSPs

Hi, I start to work on FPGA Embedded system. I am trying to port the MonstaVista Linux on the system. First I built the...

0 comments posted 19yrs

posted by airthang

0 comments posted 19yrs posted by airthang

How to get ISE to create a _bd.bmm file for BRAM initialization

I have an XPS/ISE project for a Xilinx Virtex II Pro. The XPS design is called PPC_DDR and is instantiated on a top lev...

5 comments posted 19yrs

posted by sgfallows

5 comments posted 19yrs posted by sgfallows

SDRAM in SPARTAN 3E

Help!!!!!!!!! Hi, How can I write data into the ddr sdram with Microblaze and the OPB DDR. The SDRAM is 16MX16 and I ha...

0 comments posted 19yrs

posted by pbantunez

0 comments posted 19yrs posted by pbantunez

query

Hi I am working in a design.I am using altera cyclone IC.My design works fine.One problem is whenever it is brought nea...

2 comments posted 19yrs

posted by vsrpkumar

2 comments posted 19yrs posted by vsrpkumar

CMI Coder/ Decoder

Hello, did anyone know how to realize a CMI Coder/Decoder in a FPGA (preferred in VHDL). Thanks for answers an tipps. Vo...

1 comments posted 19yrs

posted by jreeg

1 comments posted 19yrs posted by jreeg

How does FPGA tools infer FIFO

In the presence of numerous styles for designing asynchronous FIFOs, how does FPGA synthesis tools infer the FIFO specif...

8 comments posted 19yrs

posted by ashish.dobhal

8 comments posted 19yrs posted by ashish.dobhal

Complex mixer

Hello, I learned that when a signal is multiplied by an IQ signal, the signal can be down sampled by 2. So assume that...

1 comments posted 19yrs

posted by ma

1 comments posted 19yrs posted by ma

GUI Based vs. Manual Instantiation of Components

Hello, I'm just curious whether people have preference when instantiating complex modules (i.e. modules with lots of pa...

1 comments posted 19yrs

posted by martin8356449

1 comments posted 19yrs posted by martin8356449

more of ERROR:MapLib:661

Hi guys, I saw another thread with the same topic. but my situation is abit different. let me explain myself 1) I am us...

2 comments posted 19yrs

posted by chrisdekoh

2 comments posted 19yrs posted by chrisdekoh