This is what I had in the ucf -
SYSTEM_JITTER = 300 ps;
>
> NET fpga_clk100 TNM_NET = TNM_fpga_clk100;
> TIMESPEC TS_fpga_clk100 = PERIOD TNM_fpga_clk100 10 ns HIGH 50 %
> INPUT_JITTER 300 ps;
>
This is what I saw in the timing report (ISE 8.1.03)
Requirement: 10.000ns
> Data Path Delay: 5.399ns (Levels of Logic = 6)
> Clock Path Skew: 0.000ns
> Source Clock: CLOCK100 rising at 0.000ns
> Destination Clock: CLOCK100 rising at 10.000ns
> Clock Uncertainty: 0.260ns
How did the timing analyzer figure out Clock uncertainity was 260pS? Input clock goes to a DCM and the 1x output is used as CLOCK100.
I understand input, system and DCM jitter values are added quadratically. I am not able to get a resultant jitter value of 520pS (so we get 260pS subtracted from clock).