How does FPGA tools infer FIFO

In the presence of numerous styles for designing asynchronous FIFOs, how does FPGA synthesis tools infer the FIFO specified in RTL?

Thanks in advance.


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I know of no tool that infers FIFOs, async or synchronous.

Tools infer shift registers and dual-port memories (1 Write, 1 or more Reads) fine. Shift registers can be used in FIFOs. The FIFOs still need coding for address control and flag generation. Without that coding there would be no chance of inference. Since there are so many ways to code the address and control, there probably is no standard inference. If the architecture supports hard FIFOs, instantiate them or generate them from the vendor's tools.

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You must be using very primitive tools. Altera, Xilinx and Synplify (and probably most other major players) certainly do.

As to the original question there probably aren't really that many 'styles' as you may think. One time through whatever part of the tool chain it is that takes the raw source code and converts it to something equivalent but easier for the downstream tools to chew on and those supposedly numerous styles likely all pop out looking the same. Remember, no matter how you code it, the functionality of the fifo isn't changing.

After all, there are many ways to code just a flip flop and the tools can recognize all of those as well so you could rightly ask the same question about how the tools detect a flip flop.


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As far as I know they don't. That would be quite an accomplishment. I quickly checked Synplify Premiere 8.6.2 manual and there was nothing about inferring FIFOs. Also Mentor Precicsion 2006a Synthesis Style Guide did not tell about fifo inference. And also Xilinx 8.2i xst manual did not have any text about fifo inferring. Could you point me to the right page in manuals?

Completely other thing is lpm_fifo and different DW_*fifo* components. But they must be instantiated directly. Same applies to coregen, altera megafunctions etc.


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Kim Enkovaara





about fifo

But they

megafunctions etc.

I agree with Kim. The Altera Quartus tool help shows several ways o instantiating FIFO "macros", but apparently none of inferring one Inferring counters, shift registers and the like is easy, but I can' imagine how to do so for a FIFO. I've had quite enough difficult inferring a ROM...

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Show me... What tool (and what code!) infers a FIFO from RTL functional code?

Today's latest tools can infer _memories_ from rtl functional descriptions, even dual port ones, but not FIFOs.

There aren't any yet that can even infer the port size changing hardware built into some block rams. You can roll your own, but it will use luts, etc. to build the extra hardware, not use the built-in features of the memory primitive.


KJ wrote:

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I can *design* a fifo by inferring dpram and counters. The only reason I can't infer the vendor fifos exactly is that the vendors don't want to give away the source code for such a template.

-- Mike Treseler

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Mike Treseler

KJ schrieb:

Hmm. How about the naive way to code a flip-flop with enable in vhdl: if rising_edge(clk) and enable='1' then q VHDL transformations by XML and XSLTs. But the VHDL compiler vendors apparently do not care.

Kolja Sulimma cronologic

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Kolja Sulimma

Gated clocks are well understood and supported by high-end synthesis tools like Precision and Synplify. If you synthesis the above circuit the enable gets connected to the FF CE input.


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