Resource estimation

Dec 15, 2006 2 Replies
T

Hi,



I'm currently preparing a design for a V4 sx55, of course it shall do a lot of signal processing. Against this background I estimate the resources needed. The FIR compiler provides the number of DSP-Slices and BRAMs, furthermore I use grep across the vhdl simulation model to count the number of FDs. Here I'm surprised that my filter shall need 1300 FD/FDR/FDSE/... Because I have to implement tens of filters it wouldn't fit. Does the number of FD* instances within the simulation file fit the number of real used FDs? I fear it:-(. If not, how can I obtain the real number of used Slices/FDs?



Bye Tom


Vote
Twitter Facebook LinkedIn
S

Hi Tom, I fear it too! Do you realise that you can trade off size against sample rate in an FPGA? You could search for "distributed arithmetic" for more information. HTH, Syms.

Vote
Twitter Facebook LinkedIn
R

If your sample rate is several times slower than the acheivable clock rat of the FPGA, you can time-multiplex the multipliers.

If you are running out of flip-flops (registers) that is a more seriou matter. You need to come up with a less register-intensive implementation I suspect that the generated code is not very efficient, and you may hav to do it "by hand".

I had similar problems with an Altera part. Only took me about 3 months t design something that fitted. ;-)

Vote
Twitter Facebook LinkedIn

Join the Discussion

Have something to add? Share your thoughts — no account required.

Didn't find your answer?

Ask the community — no account required