I'm currently preparing a design for a V4 sx55, of course it shall do a lot of signal processing. Against this background I estimate the resources needed. The FIR compiler provides the number of DSP-Slices and BRAMs, furthermore I use grep across the vhdl simulation model to count the number of FDs. Here I'm surprised that my filter shall need 1300 FD/FDR/FDSE/... Because I have to implement tens of filters it wouldn't fit. Does the number of FD* instances within the simulation file fit the number of real used FDs? I fear it:-(. If not, how can I obtain the real number of used Slices/FDs?