Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15255 Threads Posts
to

Worth reading in Field-Programmable Gate Arrays

more of ERROR:MapLib:661

Hi guys, I saw another thread with the same topic. but my situation is abit different. let me explain myself 1) I am us...
2 comments posted 19yrs
posted by chrisdekoh
2 comments posted 19yrs posted by chrisdekoh

Ones' complement addition

Hi, I'm trying to devise an efficient method to generate a ones' complement sum of two 16 bit integers in a single cycl...
13 comments posted 19yrs
posted by Ih8teSpam
13 comments posted 19yrs posted by Ih8teSpam

Maplib Error 661.

Hi, I am getting this error while implementing my design with the xilinx ise tool Using target part "2v6000ff1152-4". M...
2 comments posted 19yrs
posted by jitendrakumawat
2 comments posted 19yrs posted by jitendrakumawat

Energy consumption estimation of Virtex-4

Hi, What would be the energy consumption of a V4-LX100 where 80% of the logic is used? About 20% of that logic is workin...
2 comments posted 19yrs
posted by taileb.mehdi
2 comments posted 19yrs posted by taileb.mehdi

IQ multiplier

Hello, I learned that when a signal is multiplied by an IQ signal, the signal can be down sampled by 2. So assume that...
8 comments posted 19yrs
posted by ma
8 comments posted 19yrs posted by ma

electrical interface problem LVPECL - LVDS multi-inputs

Hi there, I'm currently having a serious problem: I got an LVPECL clock synthesizer and I want to connect it to several...
4 comments posted 19yrs
posted by diebombeausdemwesten
4 comments posted 19yrs posted by diebombeausdemwesten

NOR Flash Controller

Hi all, I have a requirement to implement a NOR flash controller in a Spartan-3E. The interface will be 32-bits and wil...
6 comments posted 19yrs
posted by shareef.jalloq
6 comments posted 19yrs posted by shareef.jalloq

BLVDS_25 @ SPARTAN3

Hi Folks, I'm using the BLVDS_25 IO standard for some in/outs in a differential Bus System where the differential bus L...
2 comments posted 19yrs
posted by
2 comments posted 19yrs posted by

FPGA : Async FIFO, Programmable full

Hi In designing asynchronous FIFOs we have to use Gray code read/write pointers. And while using gray code I know how t...
28 comments posted 19yrs
posted by pbijoy
28 comments posted 19yrs posted by pbijoy

ANNC: Static Timing Analysis Webcast

Lattice is holding a webcast tomorrow Wednesday, December 13, "Static Timing Analysis Techniques for FPGAs." The presen...
0 comments posted 19yrs
posted by bart.borosky
0 comments posted 19yrs posted by bart.borosky

Next Xilinx starter Kit

Hello everybody ! Does someone know when the next Xilinx Starter Kit is coming out ? I think the current one is from Apr...
0 comments posted 19yrs
posted by nfinity
0 comments posted 19yrs posted by nfinity

ISP interface

Hi, I'm looking for some information on the proprietary ISP interface used by Lattice (specifically in the ispGDS22 dev...
4 comments posted 19yrs
posted by david.fussell
4 comments posted 19yrs posted by david.fussell

Camera Link to XUP V2Pro Board

Hello, I'm wanting to perform some image processing on a development boar available at my university, Xilinx University...
1 comments posted 19yrs
posted by mjp500
1 comments posted 19yrs posted by mjp500