Hello,
I learned that when a signal is multiplied by an IQ signal, the signal can be down sampled by 2. So assume that I have a signal that samples at 100MS and I multiplied it by an IQ signal. Then I can down sample each I and Q to 50MS. How is it working? Do I need a filter before down sampling? Or can I down sample without any filtering? Any example design that show how I can do this preferably in FPGA?
Best regards
Yes, no, maybe.
Yes, if the conditions are right.
No, if you're too simpleminded about it.
Maybe you can downsample even more.
The Nyquist/Shannon theorem states that you need samples at a rate of
2*fo to accurately replicate a signal with a bandwidth of fo. It doesn't say this has to be straight sampling. So in the case of I & Q modulation you are getting two channels, which means you should be able to send the pairs at half the rate.A signal that 'fits' a 100MS/sec rate will have no significant energy above 50MHz. With no other knowledge of the signal, the smartest I & Q demodulation that you could do would be to use a carrier frequency of
25MHz. This means that your I & Q carrier channels would goI: 1 0 -1 0 1 0 -1 0
Q: 0 -1 0 1 0 -1 0 1
In this case, all you have to do to 'downsample' is discard the samples where the carrier is zero.
Frankly, unless you need to do processing on the I & Q channels I don't see much value in this.
What you _can_ do with I & Q downsampling is note that for any given _bandwidth_ of signal you can I & Q downconvert, then sample with half of the sampling rate that you could have used if you had just used undersampling -- and your analog filtering task is much easier.
After the sampling is done, however, you spin off into pointless mathematical pondering that don't help you get product out the door.
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