Field-Programmable Gate Arrays

Post PAR simulation for RAM Block implementations

Hello Sir, I'm trying to simulate a design involving Block RAM implemented using core generator. Please consider the ex...

4 comments posted 19yrs

posted by veeresh8210

4 comments posted 19yrs posted by veeresh8210

No results show up after "dow" and "con" in hypertrm

Hi, all I am a student in Beihang University in Beijing, P.R.China. I just started to learn to build a system uClinux o...

0 comments posted 19yrs

posted by sunrui82

0 comments posted 19yrs posted by sunrui82

Spartan 3E Not enough block ram.

I trying to port a design (video scaler) from Virtex 4 to Spartan 3E. Currently having trouble with not enough block ra...

18 comments posted 19yrs

posted by csoon

18 comments posted 19yrs posted by csoon

A suggestion for a new input interface for functions in VHDL: XOR(a0, a1, ...)

Hi Lewis, I have a suggestion on VHDL function interface. Here is a point: ('-' is used to simplify the 'downto') R(63-0...

15 comments posted 19yrs

posted by wtxwtx

15 comments posted 19yrs posted by wtxwtx

RISC implementation questions

Hi there I have some general question for implementing a general RISC architecture. I have coded so far the fetch, deco...

6 comments posted 19yrs

posted by grabherp23

6 comments posted 19yrs posted by grabherp23

Minimal pins for JTAG configuration

Hi, I built a PCB with a spartan3-xc3s400 TQ144 and tried configuring it with the simple JTAG parallal cabel III from x...

7 comments posted 19yrs

posted by jidan1

7 comments posted 19yrs posted by jidan1

how to read a sequence of video

hi , please i want some informations about reading videos using VHDL : how to input videos then to treat it? please i wa...

9 comments posted 19yrs

posted by abaidik

9 comments posted 19yrs posted by abaidik

Quartus warning messages reagarding timming and latchs

Dear users Thank you for your reply. I found that my problem lies in the state machine it self, so i basically removed...

1 comments posted 19yrs

posted by djoshi

1 comments posted 19yrs posted by djoshi

Delta Sigma A/D's integrated in FPGA's

Why don't you FPGA guys put delta sigma A/D's in future devices ? The good thing about a delta sigma A/D is the resolut...

1 comments posted 19yrs

posted by ray

1 comments posted 19yrs posted by ray

Small memories in Cyclone

Hi I am about to start on a design that will need a number of smallish memories. i.e. 8 deep x 16 wide shift registers,...

3 comments posted 19yrs

posted by mikefbase-google

3 comments posted 19yrs posted by mikefbase-google

Where is Open Source for FPGA development?

Many engineers today have Linux on Desktop as main-OS. Many engineers today use Open Source products because of their q...

34 comments posted 19yrs

posted by psihodelia

34 comments posted 19yrs posted by psihodelia

help needed

Dear Sir I am using Quartus by ALtera, i have made my design using VHDL and have ran it on model sim, the basic design...

7 comments posted 19yrs

posted by djoshi

7 comments posted 19yrs posted by djoshi

Tool to convert ISE project into makefile? (for Linux)

Hi All, I'm looking for a tool, or a method to convert the ISE project into a makefile, which I could run remotely with...

2 comments posted 19yrs

posted by wzab

2 comments posted 19yrs posted by wzab

Altera memory init file (.hex/.mif) generation using gcc objcopy - how to change base address??

Hi, I would like to load a on-chip ROM in a Altera Stratix device with the data produced by the linker script shown bel...

1 comments posted 19yrs

posted by edmond.cote

1 comments posted 19yrs posted by edmond.cote

convertion real to std_logic_vector

Hi , please my problem is how to use real constant for example 0.1913 and multiply it with an std_logic_vector(7 downto...

2 comments posted 19yrs

posted by abaidik

2 comments posted 19yrs posted by abaidik