Latest threads in Field-Programmable Gate Arrays

Where is MIG 1.7???

MIG 1.7 is already cited in the new versions of DDR2 SDRAM related application notes. There are also a few answer record...

3 19yrs

taileb.mehdi

3 19yrs taileb.mehdi

FPGA board with multiple Ethernet connections (Gigabit Ethernet)

Hi, I am searching for an FPGA board having multiple gigabit ethernet connectivity support on it. To be more precise, I...

2 19yrs

sheikh.m.farhan

2 19yrs sheikh.m.farhan

Post PAR simulation for RAM Block implementations

Hello Sir, I'm trying to simulate a design involving Block RAM implemented using core generator. Please consider the ex...

4 19yrs

veeresh8210

4 19yrs veeresh8210

No results show up after "dow" and "con" in hypertrm

Hi, all I am a student in Beihang University in Beijing, P.R.China. I just started to learn to build a system uClinux o...

0 19yrs

sunrui82

0 19yrs sunrui82

Spartan 3E Not enough block ram.

I trying to port a design (video scaler) from Virtex 4 to Spartan 3E. Currently having trouble with not enough block ra...

18 19yrs

csoon

18 19yrs csoon

A suggestion for a new input interface for functions in VHDL: XOR(a0, a1, ...)

Hi Lewis, I have a suggestion on VHDL function interface. Here is a point: ('-' is used to simplify the 'downto') R(63-0...

15 19yrs

wtxwtx

15 19yrs wtxwtx

RISC implementation questions

Hi there I have some general question for implementing a general RISC architecture. I have coded so far the fetch, deco...

6 19yrs

grabherp23

6 19yrs grabherp23

Minimal pins for JTAG configuration

Hi, I built a PCB with a spartan3-xc3s400 TQ144 and tried configuring it with the simple JTAG parallal cabel III from x...

7 19yrs

jidan1

7 19yrs jidan1

how to read a sequence of video

hi , please i want some informations about reading videos using VHDL : how to input videos then to treat it? please i wa...

9 19yrs

abaidik

9 19yrs abaidik

Quartus warning messages reagarding timming and latchs

Dear users Thank you for your reply. I found that my problem lies in the state machine it self, so i basically removed...

1 19yrs

djoshi

1 19yrs djoshi

Delta Sigma A/D's integrated in FPGA's

Why don't you FPGA guys put delta sigma A/D's in future devices ? The good thing about a delta sigma A/D is the resolut...

1 19yrs

ray

1 19yrs ray

Small memories in Cyclone

Hi I am about to start on a design that will need a number of smallish memories. i.e. 8 deep x 16 wide shift registers,...

3 19yrs

mikefbase-google

3 19yrs mikefbase-google

Where is Open Source for FPGA development?

Many engineers today have Linux on Desktop as main-OS. Many engineers today use Open Source products because of their q...

34 19yrs

psihodelia

34 19yrs psihodelia

help needed

Dear Sir I am using Quartus by ALtera, i have made my design using VHDL and have ran it on model sim, the basic design...

7 19yrs

djoshi

7 19yrs djoshi

Tool to convert ISE project into makefile? (for Linux)

Hi All, I'm looking for a tool, or a method to convert the ISE project into a makefile, which I could run remotely with...

2 19yrs

wzab

2 19yrs wzab

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