Delta Sigma A/D's integrated in FPGA's

Why don't you FPGA guys put delta sigma A/D's in future devices ?

The good thing about a delta sigma A/D is the resolution/bandwidth tradeoff selected by the digital post-filter. And if you already have a >3GBit serdes, you maybe could do a continuous time delta sigma modulator with similar area, er even combine it with a serdes. National has a continuous time delta sigma A/D with 14 Bit at 40MSPS.

Again, the good thing about it would be, that the tradeoff between resolution / bandwidth can easily be selected by post-filtering the bitstream. Resolutions from 6-16Bit's and 200MSPS - 1MSPS seem possible.

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