I'm trying to simulate a design involving Block RAM implemented using core generator. Please consider the example "Dual Port Block RAM v6.1" at
I generated an empty test bench for this design. I'm able to do PAR Simulation on virtex 2. When I tried same on virtex 4, Modelsim XE simulator is giving error message saying two generics"en_ecc_read", and "en_ecc_write" are not defined.
My tool set is: Tool : ISE 7.1 Simulator : Modelsim XE III/Starter 6.0a
Can you please help me to find the reason?
Thanks and Regards, Veeresh