Post PAR simulation for RAM Block implementations

Hello Sir,

I'm trying to simulate a design involving Block RAM implemented using core generator. Please consider the example "Dual Port Block RAM v6.1" at

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I generated an empty test bench for this design. I'm able to do PAR Simulation on virtex 2. When I tried same on virtex 4, Modelsim XE simulator is giving error message saying two generics"en_ecc_read", and "en_ecc_write" are not defined.

My tool set is: Tool : ISE 7.1 Simulator : Modelsim XE III/Starter 6.0a

Can you please help me to find the reason?

Thanks and Regards, Veeresh

Reply to
veeresh
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Hello Sir,

I'm trying to simulate a design involving Block RAM implemented using core generator. Please consider the example "Dual Port Block RAM v6.1" at

formatting link

I generated an empty test bench for this design. I'm able to do PAR Simulation on virtex 2. When I tried same on virtex 4, Modelsim XE simulator is giving error message saying two generics"en_ecc_read", and "en_ecc_write" are not defined.

My tool set is: Tool : ISE 7.1 Simulator : Modelsim XE III/Starter 6.0a

Can you please help me to find the reason?

Thanks and Regards, Veeresh

Reply to
veeresh

Hi Vereesh,

The problem you are running into is because the version of the MXE libraries are not matching with your ISE version. Please ensure that the two match. Ideally you want to use ISE 7.1i SP3 and the MXE libraries for SP3 and the IPUpdate and then try this again. It will work correctly.

Also note that when you download the libraries it says that the files have to be installed in order. What this means is that always download the latest library for that ISE version based on the time stamp on the download page.

Thanks Duth

PARSimulationon virtex 2. When I tried same on virtex 4, Modelsim XE

Reply to
Duth

Hello Sir,

Reply to
veeresh

Hello Sir,

Sorry for late reply, I couldn't check the group last week. Now I'm able to simulate the memory block in virtex also. I updated the xilinxcorelib libraries to updated ones, for which, the link was given in a readme.txt for project at

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Thanks for your k> Hello Sir,

Reply to
veeresh

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