Field-Programmable Gate Arrays

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shift register with distributed ram

is it possible to implement a serial in , parellel out shift register from xilinx distributed ram? any guidance is appre...
13 comments posted 19yrs
posted by manusha
13 comments posted 19yrs posted by manusha

Amphion IP MPEG2 Video DecoderCores

Has anybody ever used the Amphion CS6651 Cores targeted for either Xilinx or Altera FPGAs? I am currently using the Vid...
0 comments posted 19yrs
posted by amitpatel130
0 comments posted 19yrs posted by amitpatel130

iMPACT:CRC Error bit is NOT 0

Hi everybody, I am using XSA-3S1000 v1.0 and XStend v3.0. Tools are Xilinx ISE 8.1i and EDK 8.1i. I created a simple pr...
0 comments posted 19yrs
posted by tranxuantoan
0 comments posted 19yrs posted by tranxuantoan

Custom IP ports to be used as GPIOs

Hi, I have attached my custom IP to the OPB bus. The Custom IP contains ports which should directly interact with the o...
2 comments posted 19yrs
posted by sandip.gaikwad
2 comments posted 19yrs posted by sandip.gaikwad

Flash memmory model

Hi all, In my new firm we are planning to develop a flash model. What i want to know is that is there any need for such...
3 comments posted 19yrs
posted by vssumesh_asic
3 comments posted 19yrs posted by vssumesh_asic

problem while using if or case statements

hai , i am vishnu, i am doing my project in verilog using state machine, while using if or case statements i am getting...
1 comments posted 19yrs
posted by ravipativishnu
1 comments posted 19yrs posted by ravipativishnu

IEEE 802.3 Ethernet MAC implemetation in FPGA

When I am sending some frame from the PC to MAC implemented in the ML-402 board, It receives the whole frame with prope...
1 comments posted 19yrs
posted by rits.desai
1 comments posted 19yrs posted by rits.desai

URGENT HELP NEEDED: LVDS

Hi everybody! I felt in a very strange situation: I'm working with an FPGA BOARD: -2 Virtex-4LX -1 Quick LVDS bus betwe...
5 comments posted 19yrs
posted by taileb.mehdi
5 comments posted 19yrs posted by taileb.mehdi

multiple clock domain issues

Few doubts I would like to get clarified, 1. Weather synchronizers are required for control signals only or for data si...
2 comments posted 19yrs
posted by krishna.janumanchi
2 comments posted 19yrs posted by krishna.janumanchi

Parallel Cable IV in Spartan 3E???

I am trying to configure Spartan 3e (Starter Kit) with a Parallel Cable IV (J28) with flying leads instead of USB. The...
5 comments posted 19yrs
posted by pbantunez
5 comments posted 19yrs posted by pbantunez

Matrix inversion in FPGA

Hi all, I am working on a project which needs matrix inversion (dense matrix) of order 40x40 with floating point number...
0 comments posted 19yrs
posted by nsrrsn
0 comments posted 19yrs posted by nsrrsn

Digital AM/FM Receiver - Systemic Question

Hi There! I did start a post earlier with the title " Digital AM/FM Receiver", and I'm starting one again in continuati...
1 comments posted 19yrs
posted by saurster
1 comments posted 19yrs posted by saurster

Looking for resources on timing analysis

I have been doing FPGA design work for a few years now and must admit that timing analysis scares me because it is some...
4 comments posted 19yrs
posted by FPGAEngineer
4 comments posted 19yrs posted by FPGAEngineer