Latest threads in Field-Programmable Gate Arrays

Altera memory init file (.hex/.mif) generation using gcc objcopy - how to change base address??

Hi, I would like to load a on-chip ROM in a Altera Stratix device with the data produced by the linker script shown bel...

1 19yrs

edmond.cote

1 19yrs edmond.cote

convertion real to std_logic_vector

Hi , please my problem is how to use real constant for example 0.1913 and multiply it with an std_logic_vector(7 downto...

2 19yrs

abaidik

2 19yrs abaidik

shift register with distributed ram

is it possible to implement a serial in , parellel out shift register from xilinx distributed ram? any guidance is appre...

13 19yrs

manusha

13 19yrs manusha

Amphion IP MPEG2 Video DecoderCores

Has anybody ever used the Amphion CS6651 Cores targeted for either Xilinx or Altera FPGAs? I am currently using the Vid...

0 19yrs

amitpatel130

0 19yrs amitpatel130

iMPACT:CRC Error bit is NOT 0

Hi everybody, I am using XSA-3S1000 v1.0 and XStend v3.0. Tools are Xilinx ISE 8.1i and EDK 8.1i. I created a simple pr...

0 19yrs

tranxuantoan

0 19yrs tranxuantoan

EDK and Custom Peripheral: error occur when generating bitstream

hi all, first, i am sorry for my poor English. i use EDK 7.1i and ISE 7.1i. imported custom peripheral with PLB Master...

11 19yrs

lphplab

11 19yrs lphplab

Custom IP ports to be used as GPIOs

Hi, I have attached my custom IP to the OPB bus. The Custom IP contains ports which should directly interact with the o...

2 19yrs

sandip.gaikwad

2 19yrs sandip.gaikwad

Flash memmory model

Hi all, In my new firm we are planning to develop a flash model. What i want to know is that is there any need for such...

3 19yrs

vssumesh_asic

3 19yrs vssumesh_asic

problem while using if or case statements

hai , i am vishnu, i am doing my project in verilog using state machine, while using if or case statements i am getting...

1 19yrs

ravipativishnu

1 19yrs ravipativishnu

IEEE 802.3 Ethernet MAC implemetation in FPGA

When I am sending some frame from the PC to MAC implemented in the ML-402 board, It receives the whole frame with prope...

1 19yrs

rits.desai

1 19yrs rits.desai

URGENT HELP NEEDED: LVDS

Hi everybody! I felt in a very strange situation: I'm working with an FPGA BOARD: -2 Virtex-4LX -1 Quick LVDS bus betwe...

5 19yrs

taileb.mehdi

5 19yrs taileb.mehdi

multiple clock domain issues

Few doubts I would like to get clarified, 1. Weather synchronizers are required for control signals only or for data si...

2 19yrs

krishna.janumanchi

2 19yrs krishna.janumanchi

Xilinx Virtex-4 Embedded Ethernet Wrapper IP Core - HELP with UCF

Hello, I am trying to get the Virtex-4 Ethernet MAC Wrapper IP Core up and running on my Avnet Virtex-4 FX12 Mini Modul...

5 19yrs

mwiesbock

5 19yrs mwiesbock

Parallel Cable IV in Spartan 3E???

I am trying to configure Spartan 3e (Starter Kit) with a Parallel Cable IV (J28) with flying leads instead of USB. The...

5 19yrs

pbantunez

5 19yrs pbantunez

Matrix inversion in FPGA

Hi all, I am working on a project which needs matrix inversion (dense matrix) of order 40x40 with floating point number...

0 19yrs

nsrrsn

0 19yrs nsrrsn

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