help needed

Quartus defaults to the most stringent hold requirement, 0ns. A hold violation is typically due to clock skew, gated clocks, or the sourse and destination register clocked by two different clocks. Your state machine probably transistions from one state to another by CLK_H; and certain states within your state machine are probably creating strobes that are clocking registers. My guess is that the source and destination register are being clocked by two different signals thus giving you this error. If you really don't need a 0ns hold requirment on this path, you can utilize the Multicycle Hold assignment to get you by this timing warning.

Search on "hold relationship" and "Multicycle Hold timing assignment" in the help section of Quartus. These two section should help you.

Dear Rob

Thank You for your reply below.

I am still a student learning more into FPGA so please excuse me style of questioning

Quartus defaults to the most stringent hold requirement, 0ns. A hold violation is typically due to clock skew, gated clocks, or the sourse and destination register clocked by two different clocks. Your state machine probably transistions from one state to another by CLK_H; and certain states within your state machine are probably creating strobes that are clocking registers. My guess is that the source and destination register are being clocked by two different signals thus giving you this error. If you really don't need a 0ns hold requirment on this path, you can utilize the Multicycle Hold assignment to get you by this timing warning.

Search on "hold relationship" and "Multicycle Hold timing assignment" in the help section of Quartus. These two section should help you.

I got few things i need to ask.

When you say " your state machine are probably creating strobes that are clocking registers", would that mean that once i get to into a state i am asserting signal, for example the input vector to the RAM gets asserted to ceratain binary value. My design uses only one clock, so how can "My guess is that the source and destination register are being clocked by two different signals thus giving you this error" i check i am not having this problem.

Thank You very much for your help

Regards

Dharmesh Joshi

Dear Rob

I also have some states that has not commands in them. The purpose of these were to cause few clock cycle delays. Could this be a problem.

Regards

Dharmesh Joshi

unlikely

Sometimes state machines are used to create read and write strobes for memory interfaces. So, even though you are transitioning from one state to another by a CLK, a signal (ie: rd_strobe, wr_strobe, or cs (chip select)) within a certain state can be synthesized as a global signal used to clock the appropriate registers. You can use the "Resource Property Editor" to check what signals are controlling the source and destination flops that are in violation. You can also highlight the violation within the report, right click, and choose "list paths" to see the detail timing analysis on the path.

If both registers are being clocked by the same signal then you are probably dealing with either a gated clock or clock routing issue. If the clock you are using is on the global network, you can rule out clock skew caused by routing.

Again, search the help files using the topics I gave you.

"each state execute some vhdl code"

Not all VHDL is synthesizable... in fact, about 70% of the language is NOT synthesizable. In general "each state execute some vhdl code" makes it sound like you think your FPGA will run like software - it will not. You are designing a piece of hardware that runs CONCURRENTLY.... things that happen sequentially refers to HOW your hardware operates - the synthesize doesn't even know that part exists, it is trying to design concurrent hardware per your code. It is possible to decode your state and use that as an enable to some piece of hardware (In general, that's how to make things occur sequentially in an FPGA), but it is impossible to make the state machine "trigger some piece of VHDL"... that piece of VHDL, if sythesizable, defines a piece of concurrent hardware that is ALWAYS there. If your simulation really operates like you described, chances are you've written in some non-synthesizable constructs.

Seriously, not trying to bust your balls or anything - just speaking as a recent student myself. Go take a basic digital design course BEFORE you try to take that fancy FPGA Lab course. If you don't understand basic gates, registers, etc... you're never going to properly understand how synthesis works.

Good luck in your schooling

Dear Paul

When i say it executes some VHDL code , its does basic things like assert certain signal high or low. The most complicated thing it does is goes from one state to another to generate a multi bit counter.

Thanks

Regards

Dharmesh Joshi