Quartus warning messages reagarding timming and latchs

Dear users

Thank you for your reply.

I found that my problem lies in the state machine it self, so i basically removed the RAM from my project and ran the synatizer using quartus.

The warning message has slighted change but may be its caused by the same mistake

Warning: Found 80 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew

Regarding the RAMS timing what my state machine is doing is creating a vector throughout differnt stages of the process and when the vector is ready to be saved . The statemachine goes to a state that asserts the Clock input to the RAM to '1' and this is asserted 1 for one clock cycle of the clock in the state machine before returning to '0';

The other message i get is Warning: Timing Analysis is analyzing one or more combinational loops as latches Warning: Node "ramin[0]$latch" is a latch .. ... ....

Am i strucuring my VHDL code wrongly or somthing. I am using mentor graphic FPGA adavantge and have graphical created a state machine.

From what i have understood is that
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It's hard to be sure of what's going on without seeing your design, but those warning messages from Quartus are a strong indication you're not coding your VHDL in a clean way. Instead of gating the clock to your RAM, use a clock enable (safer and easier to timing analyze).

Vaughn Altera

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