Minimal pins for JTAG configuration

JJ,

You also need power and ground for the core voltage, Vccint.

And, you need Vcco for the bank that has the IO pins for the MODE selection, and configuration (even if these are unused, we still need to power the bank so the part will come out of reset and power ON).

The power ON reset requires: Vccaux, Vccint, and Vcco (on the config bank) before the part is allowed to do anything at all.

Austin

Aha, I see...thanks for the reply. Another thing, according to the datasheet the power suplies to each edge (there are 4 edges and each edge has 2 banks) of the TQ144 are connected internally together, i.e. Bank0&1, Bank2&3, etc. Each edge has 3xVCCO, 2xVCCAUX, 2xVCCINT, 4xGND. Does that mean I need to connect ONLY one pin of each power supply per edge for the FPGA to function (since they are connected internally)?

JJ

JJ,

Yes, that would be true.

With only one power pin being shared, I would not expect the part to work well when a configuration is downloaded, but for JTAG, that is all that would be needed.

Austin

With a multimeter I checked if the necesserly power supply pins and configuration pins are connected to their pads and they seem to be so. However, I might have accidently connected the pins to the pads by just pressing the pins with the multimeter probe or (worst case) the FPGA might be damaged. If the necesserly power supplies for configuration are not all connected, the POR( Power-On Reset) is activated. Is there way to test if the POR is activated or not from outside?

JJ,

If the part is connected properly, you will see the proper signal on INIT_B.

INIT_B will go high while the devices cleans out, and gets ready to try to configure, and then it will go low when cleanout is done before it starts to configure. If there is no configuration device present, then this sequence of INIT_B lets you know that the device is ready and waiting.

Also, if a master mode is selected, the CCLK pin should be running.

See page 56 of 280:

Austin

Thank you Austin for your help. I finally got to program the FPGA. The problem was on the programmer I used: Xilinx Parallel Cable 3. The strange problem with this cable has haunted me since I built it. I described the problem here:

JJ

JJ,

Sounds like you have a signal integrity problem with the cable and the interface.

I suggest using Hyperlynx from Mentor to troubleshoot, or read up on SI.

Austin