Field-Programmable Gate Arrays

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Interfacing FPGA with TTL

Hi, I am using the UP2 development board from Altera. I have programmed a simple ALU in it. I have done some hardware t...
1 comments posted 19yrs
posted by Jalen.Ong
1 comments posted 19yrs posted by Jalen.Ong

type/subtype definition in entity

I want to define a type related to entity generics, like an array in the following codes. But It seems I have no places...
3 comments posted 19yrs
posted by zhangpei
3 comments posted 19yrs posted by zhangpei

Debug monitor for Freescale MPC5200

I have put a debug monitor for the MPC5200 PPC processor for download (free for development purposes) at http://tgi-sci...
0 comments posted 19yrs
posted by dp
0 comments posted 19yrs posted by dp

License Key based on WLAN/Bluetooth MAC

Evnin' To make life easier when I decide to abandon an old Workstation to get a more powerful one... Can for example Qu...
5 comments posted 19yrs
posted by richard_uclinux_net
5 comments posted 19yrs posted by richard_uclinux_net

Matlab Simulink HDL coder generated code interface.

Hello, I read about Matlab/Simulink HDL code and did simple test with it. I couldn't understand what the meaning of por...
0 comments posted 19yrs
posted by (myname_here)_123456
0 comments posted 19yrs posted by (myname_here)_123456

Safety of bidirectional lines

Hi, I intend to wire up an Altera Cyclone 2 to a NET2272 USB controller. The bus of the NET2272 is similar to that of a...
5 comments posted 19yrs
posted by sebastien.bourdeauducq
5 comments posted 19yrs posted by sebastien.bourdeauducq

dual port memory from single port RAM.

Hi all, My ASIC design requires dual port memories(one port R/W other port only read) but there is a constraint on usin...
9 comments posted 19yrs
posted by bajajk
9 comments posted 19yrs posted by bajajk

Xilinx ISE 9.1

It seems to work better (much better than 8.1), but seems to have a few issues that make it a bit hard to use. 1/ Somet...
4 comments posted 19yrs
posted by g.eckersley
4 comments posted 19yrs posted by g.eckersley

PLB Master

Hi, I build a IPIF master with Create/Import Peripheral. I try the example write in the user_logic.vhd: -- Here's an ex...
12 comments posted 19yrs
posted by lpaulo07
12 comments posted 19yrs posted by lpaulo07

vpw/pwm controller

hi all, can anyone tell me where i can get a free vpw/pwm controller either in vhdl or verilog according to j1850 standa...
3 comments posted 19yrs
posted by ashasravanthi
3 comments posted 19yrs posted by ashasravanthi

How to design a SDIO peripheral card?

I want to design a prototype of SDIO peripheral card which is enabled with GPS function. But I have no experience in SDI...
2 comments posted 19yrs
posted by zhy.sh.cn
2 comments posted 19yrs posted by zhy.sh.cn

Xilinx LogiCore FFT 3.2

Hi All, I am using the Xilinx Core Genenator to generate the FFT core for my design. But when I tried to simulate with...
1 comments posted 19yrs
posted by espzzh
1 comments posted 19yrs posted by espzzh

OPB To Wishbone Bridge

Hi all, I am looking for an OPB to wishbone bridge to let OPB talk to my IP via wishbone in EDK. I have read some posts...
5 comments posted 19yrs
posted by sheikh.m.farhan
5 comments posted 19yrs posted by sheikh.m.farhan

combinatorial vs sequential

hi could you please explain wht is to be coded in combinatorial and wht to be coded in sequential. am bit confused Thank...
0 comments posted 19yrs
posted by lokesh.boddu
0 comments posted 19yrs posted by lokesh.boddu