I intend to wire up an Altera Cyclone 2 to a NET2272 USB controller. The bus of the NET2272 is similar to that of a parallel RAM, with address lines, bidirectional data bus, and read/write strobe signals.
I'm concerned about the electrical safety of the bidirectional data lines. If I mess up the FPGA program and assert the read strobe signal while the data lines are set as outputs, this may damage (expensive) parts, right ? Do you know of a simple way to avoid this ? Putting resistors in series on the data lines ?
Resistors is a fool-proof way of doing it as long as the necessary resistors are small enough not to have a significant effect on the data valid window in either direction.
Another possibility would be to simply set the IOB slew rate to slow and output drive current to 4-8mA. Under these drive conditions, most FPGAs can survive indefinitely long shorts (to ground or Vccio) when cooled appropriately.
Note: actual short-circuit currents will actually be higher than the current specified for the drive strength. There is a chart somewhere on Xilinx's site that specifies short-circuit currents as a function of drive strength settings. IIRC, the short-circuit currents for 8mA drive was something like 30mA.
Hi Sebastien, Normally, contention will not break the part. AFAICR, I've never damaged a part this way in the (far too) many years I've been playing this game. The I/O pins can withstand a short to ground or short to Vdd, so contention isn't going to permanently damage anything, especially if you don't leave anything long enough to get too hot. Anyway, you'll have simulated everything first, so there'll be no problem, right? ;-) I'm not entirely convinced that Daniel's suggestion will make much difference to the reliability. The current drive is set by turning on more or fewer drive transistors. By setting the part to 4-8mA, most of the drive transistors are off, but the ones that are on will still be taking the same individual current as when they are all on, so are just as likely to locally overheat. In fact, setting the drive current to a high value may protect the FPGA better as the IC it's contending against might be the current limiting device and this current will be spread over more drive transistors. Of course, the other part will then be stressed more. OTOH, the FPGA will, overall, warm up more with more power being dissipated. All in all, you're very unlikely to break anything. Whatever, simulate your design, and avoid the situation altogether! HTH, Syms.
What is slew rate? It is how fast a signal goes from one voltage to another.
What limits slew rate? Mostly path impedance, capacitance and driver strength.
IOBs use current-limited output drivers for slow slew while fast-mode current is only limited by the output drivers MOS' impedance... over 100mA per pin - a few shorts to ground with those and you can burn out the Vccio bonding wires/traces, assuming the output drivers can survive a sustained short at this power level (150-400mW each) in the first place.
It seems the slew rate is determined, as I suspected, by controlling the slew rate at the gate of the drive transistor. The gate has significant capacitance, so adjusting how hard you drive the gate will adjust the output slew rate. I think saying the slew rate depends on 'current-limiting' is a little misleading. I reckon, EMI aside, changing the slew rate setting will have bugger all effect on the OP's system when it's in contention, assuming the contention lasts for more than few ns. HTH, Syms.
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here.
All logos and trade names are the property of their respective owners.