Field-Programmable Gate Arrays

Running Xilinx 9.1 GUIs on FC6

I've been trying to launch ISE (9.1SP3) and I get this error FATAL_ERROR:Portability:Port_ExecLoaderInit.c:117:1.4 - Th...

4 comments posted 19yrs

posted by bjrosen

4 comments posted 19yrs posted by bjrosen

FPGA High speed Transceivers for source synchronus bus application

I would like to know if you have used the High speed FPGA Tranceivers for source synchronous bus application. In my app...

2 comments posted 19yrs

posted by cpandya

2 comments posted 19yrs posted by cpandya

Writing to BRAM using OPB

Hi all, I am trying to make a peripheral attached to the OPB bus. This peripheral has a BRAM block in it. The idea is t...

2 comments posted 19yrs

posted by vbhanu

2 comments posted 19yrs posted by vbhanu

Why 166Mhz DDR?

Hi, I was wondering how the number 166Mhz for DDR came up? Why not say... 200MHz/250MHz DDR? I am sure there is some th...

9 comments posted 19yrs

posted by rohit2000s

9 comments posted 19yrs posted by rohit2000s

[xilinx] par [placer] consistency

Hi! I have a [MCU] core running at 50MHz which I use for generating patterns/reading status of some other logic, mapped...

6 comments posted 19yrs

posted by iiahim

6 comments posted 19yrs posted by iiahim

Pin Count requirements with MICO32

Hallo, has anybody some pin count requirements for the Latticemico32? I know, it depends heavily on the choosen combina...

2 comments posted 19yrs

posted by bon

2 comments posted 19yrs posted by bon

How many RAM words can I implement in my Xilinx FPGA?

I would like to make a dual-port RAM inside my FPGA... I am using a Spartan 3 1000K gate model... I know it takes a pre...

3 comments posted 19yrs

posted by thesteveman_ice9

3 comments posted 19yrs posted by thesteveman_ice9

ML506 Platform Flash

Hello Has anyone figured out how to program and configure from the Platform Flash on the ML506. I have spent a lot of q...

1 comments posted 19yrs

posted by pete.dudley

1 comments posted 19yrs posted by pete.dudley

picoblaze C compiler download wanted

I was hoping to download Francesco Poderico's Picoblaze C compiler today, but unfortunately his domain is expired. Goog...

14 comments posted 19yrs

posted by eric

14 comments posted 19yrs posted by eric

SoC

Hi experts, I want to persue my PhD in SoC , would you tell me best institutes or research goroups in Europe in this are...

1 comments posted 19yrs

posted by mirzamihsan

1 comments posted 19yrs posted by mirzamihsan

Order of the synchronous operations

Consider the very simple VHDL code at the end of the message. For each clock cycle two operations are done: 1) A counte...

20 comments posted 19yrs

posted by antonio12358

20 comments posted 19yrs posted by antonio12358

Simulating LogicCores with Webpack

Is it possible to simulate logic cores with WebPack? I'm using Webpack 9.1.03i. First I tried the ISE Simulator, then t...

0 comments posted 19yrs

posted by theller

0 comments posted 19yrs posted by theller

JTAG ID code 0xFFFFFFFF

Hi, I need some help with my Altera Dev Kit (STRATIX DSP S80 Development Board Rev 1.2). I no longer seem to be able to...

3 comments posted 19yrs

posted by callmevc

3 comments posted 19yrs posted by callmevc

How do I constrain Xilinx to implement multi-cycle paths?

Due to RAM access, I calculate data on rising edge while feed into the RAM on negedge edge of clk_100m_i, which is 100M...

1 comments posted 19yrs

posted by newsreader

1 comments posted 19yrs posted by newsreader

PLB Master to communicate with the BRAM

Hi, I need to make an IPIF PLB MASTER and I have some question about this purpose, -what is the IP2IP_Addr bus ? -why t...

0 comments posted 19yrs

posted by lpaulo07

0 comments posted 19yrs posted by lpaulo07