I am currently working with a large design with long synthesis and implementation times. The design is synthesized with Precision RTL and the gate-level netlist is exported manually to Quartus II by means of an EDIF file. I use a TCL script to automate implementation, mainly to automatically tweak a few parameters.
I would like to modify my Quartus II implementation script to add a SignalTap II component on the *first* implementation pass, and I would also like to be able to assign which pins and buses I'd like to debug without having to deal with the GUI. I went through most of the documentation, and played with the GUI quite a bit, and could not manage to add the SignalTap II component without first implementing the entire design. I typically receive the "Compile the project to continue" message.
Any and all advice is appreciated, thanks for your help!