Embedding Altera SignalTap II on 1st synthesis/implementation pass

Hi,

I am currently working with a large design with long synthesis and implementation times. The design is synthesized with Precision RTL and the gate-level netlist is exported manually to Quartus II by means of an EDIF file. I use a TCL script to automate implementation, mainly to automatically tweak a few parameters.

I would like to modify my Quartus II implementation script to add a SignalTap II component on the *first* implementation pass, and I would also like to be able to assign which pins and buses I'd like to debug without having to deal with the GUI. I went through most of the documentation, and played with the GUI quite a bit, and could not manage to add the SignalTap II component without first implementing the entire design. I typically receive the "Compile the project to continue" message.

Any and all advice is appreciated, thanks for your help!

Edmond

Reply to
Edmond Coté
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Hi Edmond,

You can add in include Signal Tap II into your first pass compile by directly instantiating it in your code. There is a Signal Tap II megafunction that you can configure in the MegaWizard Plugin Manager (Tools -> MegaWizard Plugin Manager). The config options are relatively straightforward.

When you synthesize, Precision will treat the module/entity as a black box. Check out page 24 of

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51011.pdf. This describes the flow for black box instantiation with Precision.

Also, I guess you want to have signal tap in the first pass because of the long re-compile times. With the Signal Tap GUI flow, you don't have to go through a complete recompile. There is an option to add Signal Tap nodes in post-fit. (i.e. no synthesis of your original design, just an addition of the Signal Tap logic). You can do this by turning on Incremental compile in the settings dialog box (it's defaulted to on) and checking the "Incremental Compilation" in the Signal Tap GUI.

Hope this helps, FQ

Reply to
FightingQuaker1

Full Incremental Compilation is definitely turned on, but I haven't made any "LogicLock" assignments... is that actually necessary?

Anyhow, I haven't been able to get around doing ...

1 Create EDIF project from Precision RTL (scripted) 2 Enable Signal Tap II in design (unable to add nodes) 3 Perform full compile (synth + p&r).. wait 30-40 minutes.. 4 Add post-fitted nodes 5 Perform full compile.. again.. 6 GOTO 4

Also, I have been unable to add BI-DIRECTIONAL pins to signal tap without it complaining during (re)-synthesis...

Any ideas?, at this point I just want to get this to work!

Edmond

Reply to
Edmond Coté

You shouldn't have to worry about LogicLock assigments. By default your top level project forms a "Design Partition" Check in the settings dialog box to make sure "Full Incremental Compilation" is turned on. After you do that, go to the Design Partitions window ( under the Assignments menu). Make sure that the top level partition is set to Netlist type "Post-Fit". In Signal Tap, you can then turn on incremental Compilation and add your nodes post- fit. That should get you started without having to recompile this thing every time.

Also, I noticed that Quartus doesn't allow you to both instantiate signal tap into your RTL and use the GUI, so stick to either one or the other.

btw, what version of Quartus are you running?

Reply to
FightingQuaker1

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