It seems to work better (much better than 8.1), but seems to have a few issues that make it a bit hard to use.
1/ Sometimes it auto trims logic which is required - particularly when it is associated with Jtag devices. This behaviour seems unpredictable, and happens when completely unrelated logic is moved around, or even when an identical logical expression in vhdl is expressed differently. 2/ Sometimes multiple contending tristate drivers are generated when only one exists. This seems to depend on completely unrelated logic and also seems to depend on the syntax level in vhdl where the driver is declared. 3/ Routing sometimes fails, but adding a bit of extra random stuff can make it work. Sometimes a source program which fails to route on 9.1 routes quite happily on 7.1 . 4/ The random experimentation (usually tedious) to get round these problems is usually successful ,but can be very time consuming.Does anyone have any comment , or way round any of these difficulties