Field-Programmable Gate Arrays

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Lockup with Xilinx mch_opb_ddr

Hi, I'm using the mch_opb_ddr-controller V1.00c from EDK8.2 in a Microblaze design. Beside the Microblaze, another bus...
2 comments posted 19yrs
posted by acher
2 comments posted 19yrs posted by acher

does SRL exist in non-xilinx FPGAs?

Hey, Is there any non-xilinx FPGA that has the equivalent of Xilinx Virtex SRL component as a basic component logic? If...
1 comments posted 19yrs
posted by tlenomade
1 comments posted 19yrs posted by tlenomade

Anyone using the TimingAnalyzer

Hello All, Back in the 2002, I was developing a program called the TimingAnalyzer. Below is a copy of an announcement m...
0 comments posted 19yrs
posted by dfabrizio51
0 comments posted 19yrs posted by dfabrizio51

Camera Control

Hello, I have a xupv2p board and I am wanting to use this board to perform image processing from 2 camera-link based ca...
2 comments posted 19yrs
posted by mjp500
2 comments posted 19yrs posted by mjp500

How to Ask a Question

Hi - In light of a recent flameboree in these parts, I thought it might be helpful to provide a link to an article enti...
3 comments posted 19yrs
posted by bobsrefusebin
3 comments posted 19yrs posted by bobsrefusebin

Digital gain and offset correction

Hallo, which is the way to perform digital vgain and offset correction using a fpga? Thanks, Marco T.
9 comments posted 19yrs
posted by marcotoschi
9 comments posted 19yrs posted by marcotoschi

Xilinx Webpack 9.1i.03 Verilog synthesis bug?

For the combinational-logic of my state-machine, if I use an always @*, Xilinx XST erroneously optimizes/removes the lo...
2 comments posted 19yrs
posted by xilinx_user
2 comments posted 19yrs posted by xilinx_user

downto usage in EDK

Hi, I vaguely seem to remember a provision on the use of downto in EDK. I tried to dig this out before posting this wit...
3 comments posted 19yrs
posted by mloulah
3 comments posted 19yrs posted by mloulah

plb_tft_cntlr_ref in XUP

hi everybody, I'm using plb_tft_cntlr_ref IP in EDK8.1 project, based on XUP Vertex2Pro Development Board, now having s...
0 comments posted 19yrs
posted by yang_yi
0 comments posted 19yrs posted by yang_yi

PowerPC_GPIO

Has anyone measured the cycles needed for a PowerPC to output data in a GPIO port? I am using a Virtex-II Pro device and...
0 comments posted 19yrs
posted by
0 comments posted 19yrs posted by

PowerPC_DDR

I am trying to interface a PowerPC in a Virtex-II Pro device with an external DDR memory on the board. I am using the f...
0 comments posted 19yrs
posted by
0 comments posted 19yrs posted by

how to choose the perfect fpga support

hi every body, i want to implement a vhdl program into an fpga support ( the program is compressing video ), i want kno...
27 comments posted 19yrs
posted by abaidik
27 comments posted 19yrs posted by abaidik

V4FX PPC ICU data transfer timeout?

Hi. Debugging a board with V4FX12 I noticed a strange behaviour of the PPC ICU. It seems that the ICU has an undocument...
0 comments posted 19yrs
posted by jetmarc
0 comments posted 19yrs posted by jetmarc