Field-Programmable Gate Arrays

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Uart problem, xapp223 + Spartan3A

I'm using Ken Chapman's uart_tx in a Spartan3A design. The HDL compler can't find the module/primitive, so I wonder if...
1 comments posted 19yrs
posted by borge.strand
1 comments posted 19yrs posted by borge.strand

xc3sprog and spartan 3e/3a

Hi! I was successful in the past using xc3sprog to program Spartan3 (50, 200) and the associated serial flash. Can anyo...
0 comments posted 19yrs
posted by iiahim
0 comments posted 19yrs posted by iiahim

NgdBuild:604 error

Hi all, I'm implementing a design which uses ROMs. The design was synthesized under precision. I used the .edf file for...
1 comments posted 19yrs
posted by mazouz.nezhate
1 comments posted 19yrs posted by mazouz.nezhate

V5 serial link

I have been tetsing with Xilinx V5 LXT board for transceiver evaluation. Currently I am focusing on the transmitter to...
0 comments posted 19yrs
posted by cpandya
0 comments posted 19yrs posted by cpandya

JTAG_SIM_VIRTEX5

Guys I am trying to simulate the BSCAN_VIRTEX5 component. The Xilinx simulation guide, sim.pdf, says that you can insta...
2 comments posted 19yrs
posted by pete.dudley
2 comments posted 19yrs posted by pete.dudley

ISE9.1: ERROR:Place:911

When i add these 2 constraint to my UCF file: CONFIG POST_CRC = "ENABLE"; CONFIG POST_CRC_SIGNAL = "FRAME_ECC_ONLY"; I...
6 comments posted 19yrs
posted by
6 comments posted 19yrs posted by

Accessing SRAM on the Spartan-3 Starter Board

Dear All, I'm sure this question was already been posted (and answered) in this list, but I could not find a suitable a...
3 comments posted 19yrs
posted by jmariano65
3 comments posted 19yrs posted by jmariano65

Craignell - Spartan-3E DIL Module

We have now posted schematics for the 40 pin variant of Craignell on our engineering website for those interested in mo...
0 comments posted 19yrs
posted by g1
0 comments posted 19yrs posted by g1

Gain and Offset Correction

Hallo, do you know a way to perform gain and offset correction of the adc output in vhdl? Many Thanks Marco T.
4 comments posted 19yrs
posted by marcotoschi
4 comments posted 19yrs posted by marcotoschi

Darnaw1 - PGA Spartan-3E Module

We have just posted the schematics to this product and given some more details on I/O counts on our engineering website...
5 comments posted 19yrs
posted by g1
5 comments posted 19yrs posted by g1

DVI over fiber

hello I need to design DVI over FIBER my idea to do as follow DVI to data then to FPGA the FPGA will use memory sunc SD...
3 comments posted 19yrs
posted by acohen
3 comments posted 19yrs posted by acohen

ISE 9.1 Hierarchy Problem

I recently switched over to ISE 9.1 and I noticed a problem where ISE won't recognize the design hierarchy. Thinking th...
1 comments posted 19yrs
posted by networkfabulous
1 comments posted 19yrs posted by networkfabulous