Field-Programmable Gate Arrays

NgdBuild:604 error

Hi all, I'm implementing a design which uses ROMs. The design was synthesized under precision. I used the .edf file for...

1 comments posted 19yrs

posted by mazouz.nezhate

1 comments posted 19yrs posted by mazouz.nezhate

V5 serial link

I have been tetsing with Xilinx V5 LXT board for transceiver evaluation. Currently I am focusing on the transmitter to...

0 comments posted 19yrs

posted by cpandya

0 comments posted 19yrs posted by cpandya

JTAG_SIM_VIRTEX5

Guys I am trying to simulate the BSCAN_VIRTEX5 component. The Xilinx simulation guide, sim.pdf, says that you can insta...

2 comments posted 19yrs

posted by pete.dudley

2 comments posted 19yrs posted by pete.dudley

ISE9.1: ERROR:Place:911

When i add these 2 constraint to my UCF file: CONFIG POST_CRC = "ENABLE"; CONFIG POST_CRC_SIGNAL = "FRAME_ECC_ONLY"; I...

6 comments posted 19yrs

posted by

6 comments posted 19yrs posted by

Accessing SRAM on the Spartan-3 Starter Board

Dear All, I'm sure this question was already been posted (and answered) in this list, but I could not find a suitable a...

3 comments posted 19yrs

posted by jmariano65

3 comments posted 19yrs posted by jmariano65

Altera enters as second the low-cost multigigabit tranceiver FPGA scene!!

Hi http://www.altera.com/b/arriagx.html?WT.mc_id=ag_en_mx_nk_tx_1_192 After Lattice ECP2M now also Altera has announced...

0 comments posted 19yrs

posted by Antti.Lukats

0 comments posted 19yrs posted by Antti.Lukats

Craignell - Spartan-3E DIL Module

We have now posted schematics for the 40 pin variant of Craignell on our engineering website for those interested in mo...

0 comments posted 19yrs

posted by g1

0 comments posted 19yrs posted by g1

Gain and Offset Correction

Hallo, do you know a way to perform gain and offset correction of the adc output in vhdl? Many Thanks Marco T.

4 comments posted 19yrs

posted by marcotoschi

4 comments posted 19yrs posted by marcotoschi

Darnaw1 - PGA Spartan-3E Module

We have just posted the schematics to this product and given some more details on I/O counts on our engineering website...

5 comments posted 19yrs

posted by g1

5 comments posted 19yrs posted by g1

DVI over fiber

hello I need to design DVI over FIBER my idea to do as follow DVI to data then to FPGA the FPGA will use memory sunc SD...

3 comments posted 19yrs

posted by acohen

3 comments posted 19yrs posted by acohen

ISE 8.1.03: Bizarre MAP removes almost everything of my design!!!

Hi, everyone I've been stuck on this problem for a couple of days, and still couldnt figure out how this happen. I have...

2 comments posted 19yrs

posted by yao.sics

2 comments posted 19yrs posted by yao.sics

How to get 240Mhz clock (8x) using 30Mhz clock input in Virtex4

I'm restricted to 30Mhz LVDS clock input. From this, I need to generate 240Mhz to be used internally. Restriction comes...

7 comments posted 19yrs

posted by fastgreen2000

7 comments posted 19yrs posted by fastgreen2000

ISE 9.1 Hierarchy Problem

I recently switched over to ISE 9.1 and I noticed a problem where ISE won't recognize the design hierarchy. Thinking th...

1 comments posted 19yrs

posted by networkfabulous

1 comments posted 19yrs posted by networkfabulous

'EVENT (or rising_edge) static prefix requirement....

Can't figure it out... Why cant this compile: S_chan0_clk : process (reset_delayed, ch_clk_div_int) begin for k in 0 to...

5 comments posted 19yrs

posted by pauljbennett

5 comments posted 19yrs posted by pauljbennett

XILINX ISE 9.1i: DELAYCHAIN by input data

Hi, I am working on an DSP, have problem by data receiving. As listed below, xilinx ise tools build a "DELAYCHAIN" into...

0 comments posted 19yrs

posted by uvbaz

0 comments posted 19yrs posted by uvbaz