downto usage in EDK

I haven't seen anything documented, but since Microblaze and PPC use big-endian bit-numbering (bit 0 is MSB), the interfaces are normally written using 0 to n-1 rather than n-1 downto 0. This caused me a fair bit of grief on my first home-grown EDK peripheral module.

If I'm not mistaken, VHDL vector port associations and signal assignments occur in left-to right order when not explicitly stated otherwise. You can attach a 0 to 31 port on an EDK component to a 31 downto 0 port on a non-EDK component, and it will match 0 to 31, 1 to

If you're coding something specifically for use with the EDK, it's probably best to use the big-endian bit numbering to avoid unnecessary confusion.

The ordering in EDK caused me quite a headache too. I tend to use (N downto 0) for my own HDL. The following function is very handy though:

signal dataA : std_logic_vector(0 to 31); signal dataB : std_logic_vector(31 to 0);

function reverseVector (a: in std_logic_vector) return std_logic_vector is variable result: std_logic_vector(a'reverse_range); begin for i in a'range loop result((a'length-1)-i) := a(i); end loop; return result; end;

dataB

Hi

Me too :)

Me too

I use only B