Power Consumption Estimation for PCI card, any advice?

Leon,

It is good that you have all your estimates, and are looking at it carefully. All too often, the power supply is left for last.

Depending on how much risk you wish to take, and how sensitive to cost you are, and any reliability guidelines, you will see people providing exactly what they need (no margin), to a margin of 100% (supply is twice the power required).

For example, the latest Dell desktop machine I bought has "just enough" for the peripherals in it. Adding a HDI video card will require that I pull the power supply, and get a larger one. This is a real pain, as I bought the system thinking I already had the whiz-bang super digital video card in it, but I must not have clicked the right button when I configured it. Basically, Dell provides just enough to power what I ordered.

Another example, in telecom wired and wireless equipment, the power supply is usually able to deliver twice what is needed. From a reliability point of view, such a supply is unlikely to ever fail, as it is always operating far below its rating, resulting in less heat (which is the enemy of reliability).

So, there you go: from 1.0 to 2.0 of the required power is used based on what you are doing, and who your customer is.

As to the accuracy of the prediction, be prepared to increase your power supply capability: it is hard do an accurate estimation unless you know

- all of the logic states (you have a "real" set of test benches to run through the more capable software tools --- not just a spreadsheet which is only as good as your guesses as to what you are doing), and the worst case silicon numbers have been characterized (the chip you have now may not be the same as the one you get next week).

Austin

...

Also note that doubling the maximum performance of the power supply usually costs about less than 50% extra. It's worth it to have an overdimensioned power supply. 200% may be a bit far on the safe side, but it really doesn't hurt that much financially.

Best regards,

Ben

Thank you both, Austin and Ben! That's very helpful. Actually the FPGA power consumption in the table above derived fro PowerPlay Power Analyzer(a function of Quartus II). Someone told me that a margin of only 10% is need. But I think design with so small margin must base on very accurate power consumptio estimate. So it's better for me to provide a larger margin. But now my main problem is how much power the non-IC components, suc as resistors and leds on board, will consume or usually how much for th board like I am design. Maybe I could give a rough estimate, but i stil need some empirical advice.

Leon

Leon,

You are right to question a 10% claim on a power estimator accuracy.

Altera is quite vocal is claiming that their estimator is more accurate than the Xilinx estimator.

I would say to this: they are intentionally creating a controversy where none exists to draw attention away from the areas where they do not excel, and into an area where no one can prove anything!

It is a typical marketing ploy. Whenever a claim of superiority is made (BRAM, SRL16, DCM, PLL, "faster, better, cheaper" etc etc etc) the customer is being shown a story that does not talk about the items where perhaps the product is not so great.

So, is Altera's power estimator that accurate?

The question causes everyone to stop, go look for cases where the estimator is broken, create power point slides on how "bad" the tool is, etc. Quite frankly, a waster of time, but it is all in a day's work for marketeers whose job it is to promote their product, and cause customers to look at (other) short-comings of the competition.

I would give the estimate a 20% bump for what it might actually be in practice. Any one unit will be under the estimate. Only a fast corner processed part which is shipped to fill the order will come in at the high end of the estimate. Since you can not only order "typical" parts, the additional margin is absolutely necessary.

Xilinx cerated a "battle board" with a Xilinx FPGA on one side, and an Altera FGPA on the other side (xc4vlx60, 2s60). We did a identical single ended non-DCI design for both, along with some switching in the core. We demonstrated a significant signal integrity improvement in the package and PCB (the "SmartChevron(tm)" technology). We also demonstrated how the same design in both chips led to a 15 to 20 degree C power savings in V4.

Did we focus the customer's attention? Yes.

Did we choose an area (actually 2) where we excel? Yes.

Did we create a controversy that requires an Altera response? Yes.

If you did not have a design that required strong, fast, switching IOs, and you did not have a design that challenged the internal core power, and had a great deal of timing margin (frankly, the majority of designs), then these two issues were "don't cares".

Austin

Thank you, Austin!

At Altera, power estimation is important. If customers rely on accurate power estimates for making decisions on power management, thermal management, and device selection, then accuracy also matters. We vigorously test our power modeling across a large suite of customer designs to ensure accuracy and continuous improvement.

2 differences comparing estimators for Stratix III and Virtex 5 . .

- clock power should not be omitted from the estimator (even the Virtex-4 XPE includes a worksheet for clock power)

- register power should vary with toggle rate (it does for the Stratix III EPE)

We've done the technical analysis and benchmarking on the accuracy of the spreadsheet based tools. Details on power estimation and other elements of Stratix III Programmable Power Technology (if you are interested) are discussed in a recent net seminar at:

Relying on 20% margin for estimation of Altera devices is reasonable. Using consistent assumptions in early power estimators for device selection benchmarking may not be reasonable.

Dave Greenfield Altera Marketing

And,

How predictable was that?

The fact that we beat them, hands down, for power on V4, led to Altera posing the estimator as the 'issue'.

Watch the shells, and keep your eye on that (power estimator) pea: you know where it is, don't you? You will win the prize.

Unfortunately, it is the oldest scam in the book. Distract your attention, and cause you to focus where they want. This all the while they rob you blind.

They can not have it both ways: is triple oxide bad or good? If you read the Stratix 2 stuff, it is "bad" and "risky" and "unproven."

If you read Stratix 3 literature, it is "power saving" and a "breakthrough."

Imitation is the sincerest form of flattery.

Austin

Austin

Hello Leon,

The quality of a power estimate depends on many factors. Let's talk only about dynamic power, since our worst-case static power is a specification and thus pessimistic by nature.

*Models* The power models in Quartus II for our recent FPGAs are extremely detailed and are correlated against silicon with many thousands of different targeted designs. Whatever Austin may think, the models for Stratix II & Cyclone II predict dynamic power within a range of +20..-10%. We try to err on the side of slightly over- predicting power since underpredicting has worse consequences for our customers. However, this assumes that we have *perfect vectors* for the operation of your design. And designs that have very glitchy paths (for example, long XOR chains) could be over-predicted by the tools even more.

*Design Information* You've used the PowerPlay Power Analyzer on your full design, so it knows everything - synthesis, placement, routing, and bit settings. However, for people who use the Early Power Estimator spreadsheet, then it doesn't know everything -- it must make guesses for LUT functions and length/fanout of routes, and you must make guesses for block modes, etc.

*Vectors/Toggle Rates* Assuming the tools & models are of high quality, this is where the biggest source of error comes from. Did you provide vectors from a gate-level simulation of your full design? Did your vectors truly reflect the worst-case mode of operation you will encounter in the real system? If you only had partial vectors, Quartus will fill in the blanks (for example, for combinational logic between registers in RTL simulations) -- and it's fairly good at this, but this is another source of error.

Even with good models and perfect vectors, the power tools are designed primarily for estimating power dissipation for thermal design and/or battery life. When it comes to adequately sizing your supply, you begin to run into a new problem -- current transients. Vectors turn into average power over the period of simulation -- but you will have periods of time where the switching exceeds this average. But then again, you have on-chip and off-chip decoupling capacitors that filter/smooth out these spikes. There is no quick-and-easy answer here...

So at the end of the day, I can't help you with what a reasonable guard-band is to apply to determine your power supply. 2X is a number I know some customers use -- but that could be too low or horribly over-engineered. Some customers over-engineer their prototype, but downsize their supplies after characterizing the first batch without needing to respin the board design.

Sorry I can't give you a more concrete answer,

Paul Leventis Altera Corp.

Hi Austin,

I'm sure the readers of this newsgroup are shocked to hear that companies try to draw attention to their own strengths and point out competitor's weaknesses :-). Yes, we focus a lot on power, power analysis, and power estimation for the reason you suggest -- we believe we have clear advantages in this area, and we think power is an important criteria of our customers when selecting devices.

Open up you Virtex-5 estimator. Type in 20000 FFs. Set the toggle rate to 10% and clock to 200 Mhz. Then change the toggle rate to

20%. No change in power despite a change in switching activity? For that matter, where is the clock tree power? I guess bugs are expected in software, but these are fairly egregious omissions. Perhaps the tool is accurate for designs without FFs and clocks, but somehow I don't think that's a lot of your target market ;-)

Yes. All your deflections aside, I have yet to see anything from you to refute the accuracy of our estimators.

This is a fairly confusing statement. I'm not sure whether you are talking about dynamic or static power or both.

If the power tool a customer is using does not provide "Maximum" silicon characteristics, then yes, they need to bump up the *static power* portion of the estimate. How much depends on many factors, but I believe Austin's own advice in the past has been 2X from typical to maximum, and in the absence of any other information, 2X is actual not a bad guess. However, if the tool they are using has maximum or worst- case specs available, then there is no need to guardband -- the estimates already reflect the fastest they will receive. Of course, the junction temperature must be representative of the hottest conditions the chip will be operating in, since temperature also has a large impact on static power consumtion.

When it comes to dynamic power, process variation does not have a strong impact. When you select Maximum characteristics in the EPE/ Quartus, we do adjust dynamic power slightly to account for worst-case dynamic power we see on corner units. But this variation is small (a few percent). Metal cap can vary, but it varies independently between metal layers (resulting in an averaging effect). Faster transistors have very little impact on dynamic power, since the capacitance that needs to be charged is still the same, and the short-circuit current becomes shorter (transistor switches faster) but more intense (transistor pull current faster), resulting in little change in dynamic power for most circuits.

I am not familiar with the details of this particular design. Is it the same one you were showing customers that had some of our I/Os shorted to power? That was a nifty trick. Very dramatic demo.

Regardless, there will always be designs that work well on one chip vs. the other. We also have demonstrated a number of designs to customers and in various NetSeminars. Short of making our HDL & designs open to one another for critique, I doubt we will ever get agreement (or complete buy-in from our audiences) on our dynamic power demonstrations.

But what is more important in these demos is how good is estimator accuracy? At end of the day, its not only important which device consumes lower power (I think ours do, you think yours do), but can the customer figure out what that power will be early in the design cycle? Can they measure it or profile it accurately during design? Can they optimize it with the push of a button in the CAD tools as they can with Quartus?

Paul

Paul,

Yawn.

I am not playing your game. OK? You already lost. No 65nm for ONE YEAR. Now that you are (?about) to roll out S3, we see it has triple oxide, and all of the neat things we did to save power (plus a few more of dubious value).

And, with all of that? It is certainly better than S2 (funny how to sell S3 you have to admit how S2 was so bad).

But, it is not better than V5 (at least, one can't make that claim until you actually have one to test, and you know what your process variations are, and you are ONE YEAR behind, and counting!).

And, did I mention that you are ONE YEAR behind in 65nm?

Thanks, we really appreciate having had no competition for a year (and counting).

Keep up the good work.

I apologize to the newsgroup, but even when faced with the facts, I hope it is not lost on anyone how the story on S2 changed suddenly from "great low power, excellent estimator" to "it is twice as bad as the S3, because it doesn't have triple oxide, etc."

Oh, and the constant boring claims that our estimator is somehow flawed, and theirs is so much better. Better at what?

Aust> Hi Austin,

Yawn.

Hi Austin,

I'm sure everyone else in this newsgroup is tired of our endless jabbing, but I'm not, so here I go...

Multiple gate oxides is one of many standard CMOS tricks that can be used in circuits to improve power. We intentionally did not use it at

90 nm for a variety of reasons. At 65 nm, it made sense to use. So we used it. I could spew some crap about "Wow, Xilinx finally figured out how to use a low-k dielectric at 65 nm". But I won't -- I'm sure you had your reasons for not using it at 90 nm.

As for the "dubious value" techniques you refer to, I imagine you're refering to our "Programable Power Technology" feature? Being able to trade-off power for performance on a fine-grained basis in a chip seems pretty powerful to me, but what do I know. Traditionally, the way we (Altera, Xilinx) must design the FPGA is to pick spot on the performance vs. static power trade-off curve. By just playing with the transistor threshold voltage, you have a knob that directly trades off these two quantities. At 90 nm, we each picked different points on the curve -- Stratix II had somewhat higher static power (but lower dynamic power), but also kicked butt on performance. At 65 nm, Altera decided to get off that curve. Rather than picking between "slow and low power" and "fast and higher power", we picked both. Our customers get increased performance only in those circuits that need it, and really low static power everywhere else.

And is 1.0V operation the other feature of dubious value? It seems that giving our customers yet another big knob -- 1.2V vs. 1.0V -- to control performance vs. static & dynamic power, we're providing a lot of value. I certainly hope we are, since it takes a lot of good engineering to design a chip to operate well over a larger voltage range.

"65 nm" doesn't define a chip. Its features and performance do. Does Virtex-5 have DDR3 support? Does it have high performance? Great power dissipation? Superior logic density? No. So congratulations

-- you got a 65 nm chip out that was marginally better than your 90 nm offering, before we could get out a 65 nm chip that will be significantly better than what's out there.

Yes, you did. How's your low-cost 65 nm offering coming along? Anything out to compete with Cyclone III yet? Actually, have anything that comes close to Cyclone II in performance, power or cost yet?

First, you are trying to apply logic to marketing taglines -- often a fruitless exercise. Second, your logic abilities appear to be severely underdeveloped.

A) "Stratix II has lower total power than Virtex-4. Stratix II has great power estimation." B) "Stratix III is a kick-ass device. Our new power features reduce static power by over 50% from Stratix II at equivalent densities, while improving performance by 25%."

How exactly does statement B) in any way modify or invalidate any aspect of statement A)?

Remember, you moved from 90nm to 65nm, dropped the voltage, and yet increased the static power relative to Virtex-4. I'm sure you wish you could be claiming Virtex-5 had 50% the static power of Virtex-4...

Better at predicting power; that's what we design ours for at least.

Have you tried out the FF example I have suggested twice? Any answer yet on why you don't count clock power anywhere? My theory: the XPE is as much a sales tool as an engineering tool. If you can pretend your chip doesn't have clock power, then customers will think your chips have lower power than competitive offerings, and might just buy Brand X as a result.

Cheers,

Paul Leventis Altera Corp.

Thank you, Paul