Hi,
I'm using the mch_opb_ddr-controller V1.00c from EDK8.2 in a Microblaze design. Beside the Microblaze, another bus master is accessing the DDR. Since I need to avoid some deadlocks over the OPB-Bus, I've added a third MCH to the mch_opb_ddr, which my bus master is using. The protocol is also simpler and a bit faster than OPB, so it sounds like a good choice just for RAM-access. In principle it works, but it hangs during heavy traffic :-(
This happens usually during a read from my side, where the read address is put on the MCH2 along with "control"=0 and "write"=1 for one clock. But no "exists" appears, the Microblaze is dead, even DDR-RAM access over JTAG fails. On the DDR-side no access can be seen, only the refresh runs.
When I swap "my" MCH with the instruction cache-MCH, the lockup appears much earlier.
I already made sure that no address outside of the DDR-area is accessed, the timing looks good, too. I thought that one can't do anything wrong with just two control signals... To me, it looks like an arbitration issue when the whole controller stops.
Is there something special to know about the MCH/XCL and its usage? Are there issues with more than 2 MCH channels?