Xilinx Webpack 9.1i.03 Verilog synthesis bug?

For the combinational-logic of my state-machine, if I use an always @*, Xilinx XST erroneously optimizes/removes the logic, and then rips out any downstream load-logic.

reg [6:0] s_instr_category;

// The "BAD" state-machine always @* begin : state_machine //

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Xilinx user
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For the combinational-logic of my state-machine, if I use an always @*, Xilinx XST erroneously optimizes/removes the logic, and then rips out any downstream load-logic.

reg [6:0] s_instr_category;

// The "BAD" state-machine always @* begin : state_machine //

Reply to
Xilinx user

Reply to
gabor

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