Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

Sharing a single Lookup Table

I am implementing the gamma correction LUT as in https://ptpb.pw/ZwYS if I want to share a single combinatorial lookup...
1 comments posted 9yrs
posted by user123random
1 comments posted 9yrs posted by user123random

learning verilog

Hi all, I am currently learning VHDL step by step, but I noticed there are also quite a lot of projects written in veri...
7 comments posted 9yrs
posted by kristoff
7 comments posted 9yrs posted by kristoff

HW-130 Adapters

Bump. Still looking for these adapters. Please contact me if you have any. Thanks. > My project needs to program a Xili...
0 comments posted 9yrs
posted by TimRegeant
0 comments posted 9yrs posted by TimRegeant

requirement for PC for VHDL design

Hi all, I am thinking to buy a new PC (laptop, ubuntu). One of the things I want to do more in the future is FPGA desig...
27 comments posted 9yrs
posted by kristoff
27 comments posted 9yrs posted by kristoff

Lattice JED File Formats and Device Type ID Code

I have a .jed file for a design in an XP device. These devices have gone EOL and I am trying to extend my options. The...
3 comments posted 10yrs
posted by gnuarm
3 comments posted 10yrs posted by gnuarm

iCE40: I/O toggle rate, hard numbers needed

Hi all. Can someone please make my life easier by solving a dilemma? How many signal transitions per second can iCE40's...
1 comments posted 10yrs
posted by akuktin
1 comments posted 10yrs posted by akuktin

Ob Screen Display from video coming from OV7670

Dear All Could someone explain me how to make rectangle or/and text on video coming from camera. OSD for video I use Ha...
3 comments posted 10yrs
posted by abirov
3 comments posted 10yrs posted by abirov

Looking for Xilinx HW-130/HW-120 Adapters

Bump. Still looking for these adapters. Please contact me if you have any. Thanks. > My project needs to program a Xili...
0 comments posted 10yrs
posted by TimRegeant
0 comments posted 10yrs posted by TimRegeant

eliminating a DDS

I have a design that will use a DDS synthesizer to generate an internal trigger rate for a pulse generator. The chip wi...
30 comments posted 10yrs
posted by jjlarkin
30 comments posted 10yrs posted by jjlarkin

Minimal-operation shift-and-add (or subtract)

There's a method that I know, but can't remember the name. And now I want to tell someone to Google for it. It basicall...
20 comments posted 10yrs
posted by tim
20 comments posted 10yrs posted by tim

Altera USB Blaster clone driver for STM32F1xx

Does anyone have the drivers for Windows 10 64 bit use of the STM32F1xx bas ed USB Blaster clones? They are readily ava...
2 comments posted 10yrs
posted by jamesludwighorn
2 comments posted 10yrs posted by jamesludwighorn

Zero Address CPU logic

>> Nothing Fancy, that is why in my earlier post I mentioned that I don't >> have a lot of experience. I been working a...
3 comments posted 10yrs
posted by cbayona
3 comments posted 10yrs posted by cbayona

Need help finding Synario Futurenet 6.10

Anyone know where I can find this vintage software? I am looking for the verion 6.10 free with dongle not required. I t...
2 comments posted 10yrs
posted by TimRegeant
2 comments posted 10yrs posted by TimRegeant

Help me choose an FPGA to design network protocols

Hi all, I have over a decade of experience in hardware design, but almost all of it is in ASIC. I had done some FPGA pr...
22 comments posted 10yrs
posted by pinaki2
22 comments posted 10yrs posted by pinaki2

Low End FPGAs

So I'm looking at various platforms for general purpose, fairly low-end FPGAs, and it looks like the Lattice ECP5, Xili...
14 comments posted 10yrs
posted by rgaddi
14 comments posted 10yrs posted by rgaddi