pin configuration for I2C on altera Max 10 using i2c_opencores IP


I am using a max 10 FPGA, and trying to communicate with an I2C slave. I am using the HSMC connector to connect to another board where the I2C sla ve is located. I have tested the SDA and SCL lines, so I know they are mapped through the HSMC port correctly. Then I added pullup resistors to the I2C slave PCB, pu lling the line to 3.3v. However, when I program the FPGA both SDA and SCL l ines get pulled down to 1.9V, so it seems like they are driving against the pullup instead if beeing tri-stated? I have added OPNDRN primitives to the output pins and according to the synt hesis report, the output pins are configures as opendrain. Is there any oth er type of configuration that needs to be set?

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Your output structure needs to support it. In Verilog, this works:

tri1 SCL, SDA; // out to pins

// internal use signals wire SCL_in, SDA_in; wire SDA_out, SCL_out;

// hookup the pin signals assign SDA = SDA_out ? 1'bz : 1'b0; assign SCL = SCL_out ? 1'bz : 1'b0;

// grab the input values assign SCL_in = SCL; assign SDA_in = SDA;

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What is powering that output bank? If it's powered by 1.8V, are the pins compatible with higher supply voltages? 1.9V sounds like an open-drain output that's powered by 1.8V and isn't 3.3V compatible.

Tim Wescott 
Wescott Design Services 
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Tim Wescott

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