Lattice Mico32 Simulation in Modelsim

Hi,
I have written a Mico32 application in C.
Now I want to simulate my Mico32 system in the Modelsim simulator including the C application (toggling some LEDs, ISR for controling 7 SEGMENT display).
As I have found out (by reading the Mico32 HW/SW handbook) I can create a memory initialization file which is 148MByte after generation. For that I have used
the Mico32 Software Deployment Tools -> Mico32 On Chip Memory Deployment.
My quesiton: What do I have to do next to simulate it in Modelsim? The Mico32 handbooks are not very helpful concerning that point.
Thanks, Noro
Reply to
noreeli.schmidt
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Is 148MB the size of the final contents of the on chip memory? If so, you m ay be doing something very wrong; I don't think I know of any FPGA has on c hip memory anywhere near that large! C code for toggling LEDs and such shou ld not compile to such a huge file.
To simulate it, you should just need a test bench in your chosen HDL that a sserts all the inputs and hooks up all the outputs so you can see them plot ted.
In principle, if your vendor has hooked everything up right, then the pre-s ynthesis simulation should already be accounting for the program code sitti ng in your on-chip memory. Be sure to generate all the clocks and reset sig nals, if everything doesn't get a reset in the beginning of sim, modelsim t ends to leave signals in an indeterminate state rather than assuming they s hould start at some default values.
ng the C application (toggling some LEDs, ISR for controling 7 SEGMENT disp lay).
memory initialization file which is 148MByte after generation. For that I have used
co32 handbooks are not very helpful concerning that point.
Reply to
sbattazzo
But how do I get the C program sequence into my HDL design (FPGA embedded memory blocks) for functional simulation if the generated memory ini file is shooting FPGA ressources?
Reply to
noreeli.schmidt
Additional point: The .elf file which is used to generate the memory ini file has 100 KB.
Reply to
noreeli.schmidt
It is very likely that if you wish to simulate such a large program that it won't fit on FPGA resources, it may not be practical to run in the HDL simulator. Keep in mind the simulation will run many orders of magnitude slower than real time.
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Rick C
Reply to
rickman

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